Arithmetic device and neural network device

An arithmetic method using N product-sum operation circuits that each receive inputting of M common input signals, that are each set with M weight values, and that each output an intermediate signal obtained by binarizing a product-sum operation value calculated by product-sum operation of M input values and the M weight values, M being an integer of 2 or more and N being an integer of 2 or more, the M input values being represented by the M input signals, the method comprising:

• with respect to the N product-sum operation circuits,
• inverting positive/negative of each of the M input values or positive/negative of each of the M weight values set to each of the N product-sum operation circuits, at a determination timing being a timing when a given time elapses from an input timing at which the M input values have been input to the each of the N product-sum operation circuits;
• and
• outputting an output signal representing a winner product-sum operation circuit for which the product-sum operation value having a given sign and a largest absolute value is calculated among the N product-sum operation circuits, based on a delay time from the determination timing to finalization of a logic of the intermediate signal of each of the N product-sum operation circuits.

A neural network device comprising:

• a plurality of layer circuits configured to execute arithmetic operations corresponding to a plurality of layers included in a neural network,
• wherein each of the plurality of layer circuits comprises:
• N product-sum operation circuits that each receive inputting of M common input signals, that are each set with M weight values, and that each output an intermediate signal obtained by binarizing a product-sum operation value calculated by product-sum operation of M input values and the M weight values, M being an integer of 2 or more and N being an integer of 2 or more, the M input values being represented by the M input signals,
• a control circuit that inverts, with respect to the N product-sum operation circuits, positive/negative of each of the M input values or positive/negative of each of the M weight values set to each of the N product-sum operation circuits, at a determination timing being a timing when a given time elapses from an input timing at which the M input values have been input to the each of the N product-sum operation circuits;
• and
• an output circuit that outputs an output signal representing a winner product-sum operation circuit for which the product-sum operation value having a given sign and a largest absolute value is calculated among the N product-sum operation circuits, based on a delay time from the determination timing to finalization of a logic of the intermediate signal of each of the N product-sum operation circuits,
• wherein each of the N product-sum operation circuits
• starts a product-sum operation individually from the input timing and from the determination timing, and
• outputs the intermediate signal for which a propagation delay time from the start of the product-sum operation until the finalization of the logic corresponds to the absolute value of the product-sum operation value.