# US 12,093,618 B2 · Automated circuit generation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,093,618 B2 - Document ID: US12093618B2 - Status: Granted - Kind: B2 - Application number: 18/314,007 - Filed: 2023-05-08 - Published: 2023-08-31 - Granted: 2024-09-17 - Earliest claimed: 2019-05-30 - Assignees: Celera Corporation - Applicants: Celera, Inc. - Inventors: Calum MacRae; John Mason; Karen Mason - Web page: https://patentgrep.com/patent/US12093618B2 ## CPC - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/38: Circuit design at the mixed level of analogue and digital signals - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/373: Design optimisation - G06F 2111/12: Symbolic schematics - G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In some embodiments, a computer-implemented method of generating a resistor comprises receiving a first resistor value, converting the resistor value into a plurality of resistor layout segments, and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value. ## Claims ### Claim 1 A computer-implemented method of generating a resistor comprising: receiving a first resistor value; converting the resistor value into a plurality of resistor layout segments; and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value. ### Claim 2 (depends on 1) The method of claim 1, wherein a first resistor layout segment is placed at an initial position, and other resistor layout segments are placed at positions offset from the initial position. ### Claim 3 (depends on 2) The method of claim 2, wherein the offset is based on a width of each resistor layout segment. ### Claim 4 (depends on 3) The method of claim 3, wherein the offset is further based on a predefined separation between adjacent layout segments. ### Claim 5 (depends on 4) The method of claim 4, wherein the predefined separation is based on a design rule check (DRC) value. ### Claim 6 (depends on 2) The method of claim 2, wherein resistor layout segments are placed in parallel along the length of each resistor layout segment. ### Claim 7 (depends on 2) The method of claim 2, wherein resistor layout segments are rotated by an amount specified in the one or more layout placement instructions. ### Claim 8 (depends on 2) The method of claim 2, wherein resistor layout segments are successively placed along an axis according to a polarity specified in the one or more layout placement instructions. ### Claim 9 (depends on 1) The method of claim 1, wherein each resistor layout segment has a unique identifier, the method further comprising sorting the resistor layout segments based on the unique identifier and successively placing each resistor layout segment. ### Claim 10 (depends on 1) The method of claim 1, wherein a first portion of the resistor layout segments are configured in series and a second portion of the resistor layout segments are configured in parallel. ### Claim 11 (depends on 1) The method of claim 1, wherein at least a first plurality of the resistor layout segments have a same length and width. ### Claim 12 A computer system for generating a resistor comprising: one or more processors; and a non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by the computer system, cause the computer system to perform a method comprising: receiving a first resistor value; converting the resistor value into a plurality of resistor layout segments; and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value. ### Claim 13 (depends on 12) The computer system of claim 12, wherein a first resistor layout segment is placed at an initial position, and other resistor layout segments are placed at positions offset from the initial position. ### Claim 14 (depends on 12) The computer system of claim 12, wherein a first portion of the resistor layout segments are configured in series and a second portion of the resistor layout segments are configured in parallel. ### Claim 15 (depends on 12) The computer system of claim 12, wherein at least a first plurality of the resistor layout segments has a same length and width. ### Claim 16 (depends on 12) The computer system of claim 12, wherein each resistor layout segment has a unique identifier, the method further comprising sorting the resistor layout segments based on the unique identifier and successively placing each resistor layout segment. ### Claim 17 A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer system, cause the computer system to: receive a first resistor value; convert the resistor value into a plurality of resistor layout segments; and automatically place the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value. ### Claim 18 (depends on 17) The non-transitory computer-readable storage medium of claim 17, wherein a first resistor layout segment is placed at an initial position, and other resistor layout segments are placed at positions offset from the initial position. ### Claim 19 (depends on 17) The non-transitory computer-readable storage medium of claim 17, wherein a first portion of the resistor layout segments are configured in series and a second portion of the resistor layout segments are configured in parallel. ### Claim 20 (depends on 17) The non-transitory computer-readable storage medium of claim 17, wherein at least a first plurality of the resistor layout segments have a same length and width.