US 12,092,863 B2Granted

Fabrication-tolerant on-chip multiplexers and demultiplexers

AssigneeCisco Technology, Inc.

InventorsYi Ho Lee, Tao Ling, Ravi S. Tummidi, Mark A. Webster, Prakash B. Gothoskar

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Abstract

Fabrication-tolerant on-chip multiplexers and demultiplexers are provides via a lattice filter interleaver configured to receive an input signal including a plurality of individual signals and to produce a first interleaved signal with a first subset of the plurality of individual signals and a second interleaved signal with a second subset of the plurality of individual signals; a first Bragg interleaver configured to receive the first interleaved signal and produce a first output signal including a first individual signal of the plurality of individual signals and a second output signal including a second individual signal of the plurality of individual signals; and a second Bragg interleaver configured to receive the second interleaved signal and produce a third output signal including a third individual signal of the plurality of individual signals and a fourth output signal including a fourth individual signal of the plurality of individual signals.

Claims20

Dependent claims

A demultiplexer, comprising:

a first lattice filter interleaver comprising a plurality of lattice filters, each lattice filter including at least one phase delay line pair, each phase delay line of the phase delay line pair having a different dimensioning than the other phase delay line of the phase delay line pair, wherein the first lattice filter interleaver is configured to receive an input signal including a plurality of individual signals and to produce a first interleaved signal with a first subset of the plurality of individual signals and a second interleaved signal with a second subset of the plurality of individual signals;
a first Bragg interleaver configured to receive the first interleaved signal and produce a first output signal including a first individual signal of the plurality of individual signals and a second output signal including a second individual signal of the plurality of individual signals;
and
a second Bragg interleaver configured to receive the second interleaved signal and produce a third output signal including a third individual signal of the plurality of individual signals and a fourth output signal including a fourth individual signal of the plurality of individual signals.

1 more element

A multiplexer, comprising:

a first Bragg interleaver configured to receive a first individual signal of a first wavelength and a second individual signal of a second wavelength and produce a first interleaved signal including the first individual signal and the second individual signal;
a second Bragg interleaver configured to receive a third individual signal of a third wavelength and a fourth individual signal of a fourth wavelength and produce a second interleaved signal including the third individual signal and the fourth individual signal, wherein the third wavelength is between the first wavelength and the second wavelength and the fourth wavelength is greater than the first wavelength and the second wavelength;
and
a first lattice filter interleaver comprising a plurality of lattice filters, each lattice filter including at least one phase delay line pair, each phase delay line of the phase delay line pair having a different dimensioning than the other phase delay line of the phase delay line pair, wherein the first lattice filter interleaver is configured to receive the first interleaved signal and the second interleaved signal to produce a multiplexed output signal including the first individual signal, the second individual signal, the third individual signal, and the fourth individual signal.

1 more element

A device, comprising:

a first lattice filter interleaver comprising a plurality of lattice filters, each lattice filter including at least one phase delay line pair, each phase delay line of the phase delay line pair having a different dimensioning than the other phase delay line of the phase delay line pair, wherein the first lattice filter interleaver is connected on a first side to a multiplexed signal port and connected on a second side to:
a first Bragg interleaver that is connected to a first individual signal port and a second individual signal port;
and
a second Bragg interleaver connected to a third individual signal port and a fourth individual signal port.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/451,247Filed 18 Oct 2021
Published: US 2023/0119450 A120 Apr 2023
Granted: 17 Sep 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G02B 6/12007
Of the integrated circuit kind: forming wavelength selective elements, e.g. multiplexer, demultiplexer
H04J 14/0209
Arrangements therefor: multi-stage arrangements, e.g. by cascading multiplexers or demultiplexers
G02B 6/2935
Operating by wave or beam interference: mach-Zehnder configuration, i.e. comprising separate splitting and combining means
H04J 14/0208
Arrangements therefor: interleaved arrangements