Methods and apparatus for a track and hold amplifier
AssigneeSemiconductor Components Industries, LLC
InventorShankar Ramakrishnan
Life of this patent
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Abstract
Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.
Claims20
A track-and-hold amplifier circuit, comprising:
- a gain setting circuit configured to receive an input signal;
- a cascode circuit connected to the gain setting circuit;
- a capacitor comprising first and second capacitor terminals, wherein the first capacitor terminal is connected to an output node and wherein the output node is selectively connected to the cascode circuit;
- and
- an isolation circuit connected to the second capacitor terminal, the cascode circuit, and a ground node.
A track-and-hold amplifier circuit configured to receive an input signal and transmit an output signal, the track-and-hold amplifier circuit comprising:
- a gain setting circuit configured to apply a predetermined gain to the input signal;
- a cascode circuit connected to the gain setting circuit;
- a capacitor with a terminal that provides the output signal;
- and
- an isolation circuit connected to both the cascode circuit and the capacitor, wherein the isolation circuit is configured to selectively isolate transient current in the capacitor.
An amplifier circuit, comprising:
- a first circuit comprising a first impedance element connected in series with a second impedance element;
- a second circuit connected to the first circuit, wherein the second circuit comprises first and second transistors connected in series and wherein a node is interposed between the first and second transistors;
- a capacitor that is connected to an output node that is selectively connected to the second circuit;
- and
- a third circuit connected to the capacitor, the second circuit, and a ground node, wherein the third circuit comprises a clamp device connected between the node and the ground node and a switch connected between the node and the ground node.
Dependencies are inferred from the claim text.