US 12,088,322 B2 · Method and system for on-ASIC error control decoding

Abstract

There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

Claims14

Dependent claims

A memory system comprising:

a plurality of memory components;
and
a controller in communication with the plurality of memory components and configured to:
store at least one codeword read from the plurality of memory components as beats of data organized to form a memory transfer block (MTB);
and
perform error correction code (ECC) operations on the beats of data within the MTB:
wherein the ECC operations include performing (i) encoding the MTB data as a function of a data vector within each of the beats and a parity check matrix and (ii) decoding including computing a syndrome of the encoded MTB data and decoding corresponding Bose-Chaudhuri-Hocquenghem (BCH) codes;
and
wherein the performing of the encoding and decoding include vector matrix multiplication.

6 more elements

Dependencies are inferred from the claim text.

Method and system for on-ASIC error control decoding

Life of this patent

Method and system for on-ASIC error control decoding

Life of this patent

Abstract

Claims14