Analog to digital converting device and operating method thereof
AssigneesSamsung Electronics Co., Ltd., Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University)
InventorsSanggyu Park, Jaehyeong Park
Life of this patent
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Abstract
An analog-to-digital converting device configured to convert an analog signal into a digital signal, including a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal; a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal; and a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number.
Claims20
An analog-to-digital converting device configured to convert an analog signal into a digital signal, the analog-to-digital converting device comprising:
- a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal;
- a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal;
- and
- a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number,
- wherein the counter is further configured to count the counted number by counting pulses of a clock signal input to the counter.
An analog-to-digital converting device configured to convert an analog signal into a digital signal, the analog-to-digital converting device comprising:
- a comparator configured to compare comparison voltages of bits of the digital signal with the analog signal, and output comparison results;
- a successive approximation register (SAR) logic configured to store values corresponding to comparison results for the bits of the digital signal;
- a clock generator configured to generate a first clock signal for operating the comparator;
- a meta-stability detection unit configured to output a meta-stability signal based on the comparison results;
- a counter configured to count a number of comparison operations of the comparator;
- and
- a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number of the comparison operations,
- wherein the counter is further configured to count the counted number by counting pulses of a clock signal input to the counter.
An analog-to-digital converting device configured to convert an analog signal into a digital signal, the analog-to-digital converting device comprising:
- a comparator configured to perform at least one comparison operation by comparing comparison voltages of bits of the digital signal with the analog signal, and to output at least one comparison result;
- a meta-stability detection unit configured to output a meta-stability signal based on the at least one comparison result;
- a counter configured to count a number of times that the at least one comparison operation is performed;
- and
- a successive approximation register (SAR) logic configured to output the digital signal based on the at least one comparison result and the counted number,
- wherein, based on a change in the meta-stability signal, the comparator is further configured to stop the at least one comparison operation, and the counter is further configured to stop the counting, and
- wherein the counter is further configured to count the counted number by counting pulses of a clock signal input to the counter.
Dependencies are inferred from the claim text.