Calibration method for phase-locked loops and related circuit
AssigneeSTMicroelectronics S.r.l.
InventorsDavide Nicolo Fortunato, Antonino Calcagno, Marco Vinciguerra, Angelo Scuderi, Gaetano Cosentino
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Abstract
A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i−1 in the sequence.
Claims20
A method of calibrating a voltage-controlled oscillator (VCO) in a phase-locked loop circuit, the method comprising a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps with index i=1, . . . , N that produce reduced subsets of the set of candidate frequency bands, the reduced subsets having respective upper bound values, lower bound values, and central values, a central value of a subset resulting from the halving step of the index i in the sequence being a function of an average of an upper bound value and a lower bound value of a subset resulting from the halving step of index i−1 in the sequence, the method comprising:
- identifying a desired calibration frequency for the VCO, f_des_cycle, as a number of cycles counted in a reference clock signal;
- reading a current frequency value, read_freq, which is a function of a current operation frequency of the VCO;
- performing the dichotomous search by:
- storing a stored frequency value store_read_freq[i]=read_freq for i=1;
- and
- calculating a first modulus value, |f_des_cycle−store_read_freq[i]| and a second modulus value, |f_des_cycle−store_read_freq[i−1]|;
- checking whether the first modulus value, |f_des_cycle−store_read_freq[i]| is lower than the second modulus value|f_des_cycle−store_read_freq[i−1]|;
- in response to the checking yielding a positive outcome, performing a further halving step in the dichotomous search with the index i increased by one;
- or
- in response to the checking yielding a negative outcome:
- reducing by one the respective upper bound and lower bound of a current subset in the dichotomous search prior to resuming the dichotomous search in response to read_freq being higher than f_des_cycle plus a tolerance value;
- or
- increasing by one the respective upper bound and lower bound of the current subset in the dichotomous search prior to resuming the dichotomous search in response to read_freq being lower than f_des_cycle minus the tolerance value;
- and
- calibrating the VCO to a frequency resulting from the dichotomous search.
A phase-locked loop circuit comprising:
- a voltage-controlled oscillator (VCO);
- a counter configured to read a current frequency value, which is a function of a current operation frequency of the VCO;
- and
- a finite state machine configured to:
- identifying a desired calibration frequency for the VCO, f_des_cycle, as a number of cycles counted in a reference clock signal;
- receive from the counter the current frequency value;
- perform a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps with index i=1, . . . , N that produce reduced subsets of the set of candidate frequency bands, the reduced subsets having respective upper bound values, lower bound values, and central values, a central value of a subset resulting from the halving step of the index i in the sequence being a function of an average of an upper bound value and a lower bound value of a subset resulting from the halving step of index i−1 in the sequence, the dichotomous search comprising the finite state machine configured to:
- store a stored frequency value store_read_freq[i]=read_freq for i=1;
- and
- calculate a first modulus value, |f_des_cycle−store_read_freq[i]| and a second modulus value, |f_des_cycle−store_read_freq[i−1]|;
- check whether the first modulus value, |f_des_cycle−store_read_freq[i]| is lower than the second modulus value|f_des_cycle−store_read_freq[i−1]|;
- in response to the check yielding a positive outcome, perform a further halving step in the dichotomous search with the index i increased by one;
- or
- in response to the check yielding a negative outcome:
- reduce by one the respective upper bound and lower bound of a current subset in the dichotomous search prior to resuming the dichotomous search in response to read_freq being higher than f_des_cycle plus a tolerance value;
- or
- increase by one the respective upper bound and lower bound of the current subset in the dichotomous search prior to resuming the dichotomous search in response to read_freq being lower than f_des_cycle minus the tolerance value and
- apply calibration signals to the VCO to calibrate the voltage-controlled oscillator in accordance with a frequency resulting from the dichotomous search.
Dependencies are inferred from the claim text.