Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

A sub-memory system, comprising:

• a first memory rank;
• and
• a second memory rank,
• wherein the first memory rank includes:
• a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin;
• a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin;
• and
• an on-die termination control circuit configured to independently control an enable timing and a disable timing of the first on-die termination circuit and an enable timing and a disable timing of the second on-die termination circuit,
• wherein in response to the memory device receiving a read command for the first memory rank from a memory controller at a first time point, the on-die termination control circuit is configured to control the second on-die termination circuit in an enable state to be disabled after a first time period from the first time point, control the first on-die termination circuit in an enable state to be disabled after a second time period from the first time point, control the first on-die termination circuit in the disable state to be enabled after a third time period from the first time point, and control the second on-die termination circuit in the disable state to be enabled after a fourth time period from the first time point,
• wherein the first time period is shorter than the second time period, the second time period is shorter than the third time period, and the third time period is shorter than the fourth time period,
• wherein the second memory rank includes a third on-die termination circuit connected to the data pin and a fourth on-die termination circuit connected to the read data strobe pin, and
• wherein at least one of the third on-die termination circuit or the fourth on-die termination circuit is maintained enabled while at least one of the first on-die termination circuit or the second on-die termination circuit is in the disable state.

A memory device, comprising:

• a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin;
• a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin;
• and
• an on-die termination control circuit is configured to independently control an enable timing and a disable timing of the first on-die termination circuit and an enable timing and a disable timing of the second on-die termination circuit,
• wherein in response to the memory device receiving a read command from a memory controller at a first time point, the on-die termination control circuit configured to control the second on-die termination circuit in an enable state to be disabled after a first time period from the first time point, control the first on-die termination circuit in an enable state to be disabled after a second time period from the first time point, control the first on-die termination circuit in the disable state to be enabled after a third time period from the first time point, and control the second on-die termination circuit in the disable state to be enabled after a fourth time period from the first time point, and
• wherein the memory device receives at least a portion of the data signal from the memory controller through the data pin at a time of transition between the enable state of the second on-die termination circuit and the disable state of the second on-die termination circuit, and
• wherein the first on-die termination circuit is in the enable state while the memory device receives the at least a portion of the data signal.