Apparatus and method of performing erase and erase verify operations
AssigneeMicron Technology, Inc.
InventorsFulvio Rori, Chiara Cerafogli
Life of this patent
Estimating the term…
Abstract
An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.
Claims20
An apparatus, comprising:
- an array comprising a number of groups of memory cells;
- and
- a controller coupled to the array, the controller configured to, as part of an erase operation:
- perform a first erase verify on a first set of memory cells commonly coupled to an access line of the array, wherein the first erase verify includes applying a first erase verify voltage pulse having a first magnitude to the first set of memory cells;
- perform a second erase verify on a second set of memory cells commonly coupled to the access line of the array, wherein the second erase verify includes applying a second erase verify voltage pulse having a second magnitude to the second set of memory cells, and wherein the second magnitude is different than the first magnitude;
- and
- determine whether to apply an erase voltage pulse concurrently to the first set and the second set based on a result of the first erase verify and a result of the second erase verify.
An apparatus, comprising:
- an array of memory cells;
- and
- a controller coupled to the array and configured to:
- perform a first erase verify on a group of memory cells commonly coupled to an access line of the array, the first erase verify involving applying a first erase verify voltage pulse having a first magnitude to the group of memory cells;
- perform a second erase verify on the group of memory cells commonly coupled to the access line of the array, the second erase verify involving applying a second verify voltage pulse having a different magnitude than the first magnitude to the group of memory cells;
- apply a first erase voltage pulse concurrently to the group of memory cells responsive to the group failing the first erase verify and the group failing the second the second erase verify;
- and
- apply a second erase voltage pulse concurrently to the group of memory cells responsive to the group passing the first erase verify and the group failing the second erase verify.
An apparatus, comprising:
- an array comprising a number of groups of memory cells;
- and
- a controller coupled to the array, the controller configured to, as part of an erase operation:
- perform a first erase verify on a first set of memory cells commonly coupled to a first access line of the array, wherein the first erase verify includes:
- applying a first erase verify voltage pulse having a first magnitude to the first set of memory cells;
- and
- determining whether a first threshold quantity of cells of the first set fail the first erase verify;
- perform a second erase verify on a second set of memory cells commonly coupled to a second access line of the array, wherein the second erase verify includes:
- applying a second erase verify voltage pulse having a second magnitude to the second set of memory cells;
- and
- determining whether a second threshold quantity of cells of the second set fail the second erase verify, wherein the second threshold quantity is different than the first threshold quantity;
- and
- determine whether to apply an erase voltage pulse concurrently to the first set and the second set based on a result of the first erase verify and a result of the second erase verify.
Dependencies are inferred from the claim text.