Reading circuit for a pixel array

An image sensor comprising:

• an array of pixels organized in lines and columns;
• and
• a read-out circuit comprising:
• N inputs connected to N respective outputs of the array of pixels, with N being an integer strictly greater than 1;
• N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input, each analog-to-digital converter being a successive approximation register-type converter,
• wherein, in each group, the second inputs of the analog-to-digital converters of the group are:
• connected to each other,
• electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and
• configured to receive an identical first reference signal for all the analog-to-digital converters of the group;
• a first circuit configured to provide a second reference signal;
• and
• for each group, a first buffer circuit configured to receive the second reference signal and to provide the first reference signal of the group to the second inputs of the analog-to-digital converters of the group, wherein the second reference signal is a DC reference voltage.

A read-out circuit comprising:

• N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1;
• N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input,
• wherein, in each group, the second inputs of the analog-to-digital converters of the group are:
• connected to each other,
• electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and
• configured to receive an identical first reference signal for all the analog-to-digital converters of the group;
• a first circuit configured to provide a second reference signal;
• and
• for each group, a respective buffer circuit configured to receive the second reference signal and to provide the first reference signal of the group to the second inputs of the analog-to-digital converters of the group, the respective buffer circuit comprising as many follower amplifiers as there are analog-to-digital converters in the group.