Decision feedback equalizer with high input sensitivity and improved performance for signal processing

A method of providing a decision feedback equalizer (DFE), comprising:

• configuring a summer to receive a signal stream;
• providing a plurality of feedback taps including a first feedback tap;
• and
• coupling an input node of the first feedback tap to an output node of the summer,
• wherein providing the plurality of feedback taps including the first feedback tap comprises:
• configuring a pre-amplifier of the first feedback tap to be clocked by a first clock signal, wherein the pre-amplifier is configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream;
• coupling a combined latch of the first feedback tap to an output node of the pre-amplifier, wherein the combined latch comprises:
• a latch amplifier configured to be clocked by the first clock signal and a second clock signal, wherein both the first clock signal and the second clock signal are configured to be determined by a main clock of the DFE;
• a main latch configured to be clocked by the second clock signal;
• and
• a buffer amplifier configured to be clocked by an inverse signal of the second clock signal;
• and
• coupling a digital to analog converter (DAC) of the first feedback tap to an output node of the combined latch,
• wherein the first postcursor is for being provided to the pre-amplifier without being provided to the summer.

A decision feedback equalizer (DFE), comprising:

• a summer configured to receive a signal stream;
• and
• a plurality of feedback taps;
• wherein an input node of a first feedback tap of the plurality of feedback taps is coupled to an output node of the summer, and the first feedback tap comprises:
• a pre-amplifier configured to be clocked by a first clock signal, wherein the pre-amplifier is configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream;
• a combined latch configured to be clocked by the first clock signal and a second clock signal, the combined latch coupled to an output node of the pre-amplifier, wherein both the first clock signal and the second clock signal are configured to be determined by a main clock of the DFE;
• and
• a digital to analog converter (DAC) coupled to an output node of the combined latch,
• wherein the first postcursor is for being provided to the pre-amplifier without being provided to the summer.