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US 12,081,234 B2Granted
ECC memory chip encoder and decoder
AssigneeIntel Corporation
InventorKjersten E. Criss
Life of this patent
Estimating the term…
Abstract
An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
Claims24
A memory device comprising:
- error correction code (ECC) encoder logic circuitry;
- and
- ECC decoder logic circuitry to:
- read a code word from memory, the code word including data bits and ECC check bits, wherein the data bits are divided into data blocks, and
- in response to a multi-bit error limited to one of the data blocks, use an ECC code to insert mis-corrections of the multi-bit error to the code word, where, the ECC code provides for first and second error correction schemes, where the first error correction scheme inserts mis-corrections within the data block with the multi-bit error, and where, the second error correction scheme inserts mis-corrections within the ECC check bits.
2 more elements
A processor comprising:
- a processing core;
- and
- a memory controller to couple with the processing core and a memory device, wherein the memory device includes error correction code (ECC) logic circuitry to:
- detect errors in a code word from memory, the code word including ECC check bits and data divided into data blocks,
- use an ECC code to insert mis-corrections of a multi-bit error to the code word, where, the ECC code provides for first and second error correction schemes, where the first error correction scheme inserts mis-corrections within the data block with the multi-bit error, and where, the second error correction scheme inserts mis-corrections within the ECC check bits, and
- send the data to the memory controller;
- and
- wherein the memory controller is to:
- receive the data from the memory device in response to a read operation, and
- determine whether the received data has an error.
7 more elements
An apparatus comprising:
- an interface to couple with a memory controller;
- multiple memory chips;
- and
- logic circuitry to:
- read a code word from memory, the code word including data bits and error correction code (ECC) check-bits, wherein the data bits of the code word comprise multiple regions, and
- in response to a multi-bit error in one of the regions, use an ECC code having first and second error correction schemes, where, the first error correction scheme constrains errors added to the code word by the first error correction scheme within boundaries of the region with the multi-bit error, and where, the second error correction scheme constrains errors added to the code word by the second error correction scheme within the ECC check-bits.
3 more elements
A system comprising:
- a memory controller;
- and
- a memory module to couple with the memory controller, the memory module including multiple memory chips, a memory chip of the multiple memory chips including error correction code (ECC) decoder logic circuitry to:
- read a code word from memory, the code word including data bits and ECC check-bits, wherein the data bits of the code word comprise multiple regions, and
- in response to a multi-bit error in one of the regions, use an ECC code having first and second error correction schemes, where, the first error correction scheme constrains errors added to the code word by the first error correction scheme within boundaries of the region with the multi-bit error, and where, the second error correction scheme constrains errors added to the code word by the second error correction scheme within the ECC check-bits.
2 more elements
Dependencies are inferred from the claim text.