Multiphase digital frequency synthesizer with fractional division

A multiphase digital frequency synthesizer, comprising:

• a multiphase ring oscillator that is configured to provide a plurality of phased clock signals;
• a clock divider that is configured to divide a selected one of the plurality phased clock signals by an integer value and a carry value and that provides a divided clock signal;
• positive select circuitry that accumulates a positive select value with a fractional division factor for providing a first accumulated value, that performs a modulo function on the first accumulated value for providing a first modulo value, and that updates the positive select value in successive cycles of the divided clock signal using the first modulo value;
• carry circuitry that determines the carry value by dividing the first modulo value by a number of the phased clock signals and that updates the carry value in successive cycles of the divided clock signal;
• positive multiplex circuitry that selects from among the plurality of phased clock signals using the positive select value for providing a positive multiplexed clock signal;
• and
• fractional phase addition circuitry that provides a first output clock signal based on a selected one of the plurality of phased clock signals, the divided clock signal, and the positive multiplexed clock signal.