US 12,080,802 B2Granted

Semiconductor device comprising silicon and oxide semiconductor in channel formation region

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorShunpei Yamazaki

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Abstract

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Claims5

Dependent claims

A semiconductor device comprising:

a first transistor comprising silicon in a channel formation region;
and
a second transistor comprising an oxide semiconductor in a channel formation region,
wherein a first insulating layer is provided over the channel formation region of the first transistor,
wherein a first gate electrode of the first transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the first gate electrode of the first transistor,
wherein a layer comprising the channel formation region of the second transistor is provided over the second insulating layer,
wherein a third insulating layer is provided over the layer comprising the channel formation region of the second transistor,
wherein a second gate electrode of the second transistor is provided over the third insulating layer,
wherein a fourth insulating layer is provided over the second gate electrode of the second transistor,
wherein a fifth insulating layer is provided over the fourth insulating layer,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor via an opening provided in the second insulating layer, an opening provided in the third insulating layer, an opening provided in the fourth insulating layer, and an opening provided in the fifth insulating layer,
wherein the one of the source electrode and the drain electrode of the second transistor has a three-layer structure in which an aluminum layer is stacked over a first titanium layer and a second titanium layer is stacked over the aluminum layer,
wherein the first titanium layer is in contact with the layer comprising the channel formation region of the second transistor,
wherein the oxide semiconductor comprises a crystalline region, and
wherein a third gate electrode of the second transistor overlaps with the channel formation region of the second transistor and the second gate electrode of the second transistor.

13 more elements

A semiconductor device comprising:

a first transistor comprising silicon in a channel formation region;
and
a second transistor comprising an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises indium, gallium, and zinc,
wherein a first insulating layer is provided over the channel formation region of the first transistor,
wherein a first gate electrode of the first transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the first gate electrode of the first transistor,
wherein a layer comprising the channel formation region of the second transistor is provided over the second insulating layer,
wherein a third insulating layer is provided over the layer comprising the channel formation region of the second transistor,
wherein a second gate electrode of the second transistor is provided over the third insulating layer,
wherein a fourth insulating layer is provided over the second gate electrode of the second transistor,
wherein a fifth insulating layer is provided over the fourth insulating layer,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor via an opening provided in the second insulating layer, an opening provided in the third insulating layer, an opening provided in the fourth insulating layer, and an opening provided in the fifth insulating layer,
wherein the one of the source electrode and the drain electrode of the second transistor has a three-layer structure in which an aluminum layer is stacked over a first titanium layer and a second titanium layer is stacked over the aluminum layer, and
wherein the first titanium layer is in contact with the layer comprising the channel formation region of the second transistor.

12 more elements

A semiconductor device comprising:

a first transistor comprising silicon in a channel formation region;
and
a second transistor comprising an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises indium, gallium, and zinc,
wherein a first insulating layer is provided over the channel formation region of the first transistor,
wherein a first gate electrode of the first transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the first gate electrode of the first transistor,
wherein a layer comprising the channel formation region of the second transistor is provided over the second insulating layer,
wherein a third insulating layer is provided over the layer comprising the channel formation region of the second transistor,
wherein a second gate electrode of the second transistor is provided over the third insulating layer,
wherein a fourth insulating layer is provided over the second gate electrode of the second transistor,
wherein a fifth insulating layer is provided over the fourth insulating layer,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor via an opening provided in the second insulating layer, an opening provided in the third insulating layer, an opening provided in the fourth insulating layer, and an opening provided in the fifth insulating layer,
wherein the channel formation region of the first transistor does not overlap with the channel formation region of the second transistor,
wherein a first conductive layer is in contact with a top surface of the layer comprising the channel formation region of the second transistor,
wherein the third insulating layer and the fourth insulating layer comprise a region overlapping with the first gate electrode of the first transistor,
wherein the one of the source electrode and the drain electrode of the second transistor has a three-layer structure in which an aluminum layer is stacked over a first titanium layer and a second titanium layer is stacked over the aluminum layer, and
wherein the first titanium layer is in contact with the layer comprising the channel formation region of the second transistor.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/201,815Filed 25 May 2023 · continuation
Priority: JP 2009-27085728 Nov 2009
Published: US 2023/0299207 A121 Sep 2023
Granted: 3 Sep 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 30/6734
Multi-gate TFTs: having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
H10D 30/6739
Characterised by the electrode materials: conductor-insulator-semiconductor electrodes
H10D 30/6756
Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate: amorphous oxide semiconductors

Family

Application12/951,249Parent of this continuation · filed 22 Nov 2010
Application13/684,290Parent of this continuation · filed 23 Nov 2012
US 8,748,881 B2Parent of this continuation · filed 10 Jun 2014
Application14/330,597Parent of this continuation · filed 14 Jul 2014
US 8,779,420 B2Parent of this continuation · filed 15 Jul 2014
Application14/964,950Parent of this continuation · filed 10 Dec 2015
US 9,214,520 B2Parent of this continuation · filed 15 Dec 2015
Application15/882,139Parent of this continuation · filed 29 Jan 2018
US 9,887,298 B2Parent of this continuation · filed 6 Feb 2018
Application16/272,287Parent of this continuation · filed 11 Feb 2019
US 10,263,120 B2Parent of this continuation · filed 16 Apr 2019
Application16/812,546Parent of this continuation · filed 9 Mar 2020
US 10,608,118 B2Parent of this continuation · filed 31 Mar 2020
Application17/183,670Parent of this continuation · filed 24 Feb 2021
US 11,133,419 B2Parent of this continuation · filed 28 Sep 2021
US 2023/0299207 A1Pre-grant publication · published 21 Sep 2023
US 11,710,795 B2Parent of this continuation
US 2011/0127523 A1Published application
US 2013/0082256 A1Published application
US 2014/0346501 A1Published application
US 2016/0163871 A1Published application
US 2018/0166580 A1Published application
US 2019/0172952 A1Published application
US 2020/0212222 A1Published application
US 2021/0202746 A1Published application
US 12,080,802 B2This patent

From the US filing history. Foreign family members aren’t listed.