Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices

A vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:

• a III-nitride substrate having a first conductivity type;
• a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches;
• a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type;
• a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;
• a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;
• a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer;
• a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;
• a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric;
• and
• a source metal layer coupled to an upper portion of the fourth III-nitride layer.