Display panel and display device

A display panel, comprising:

• a driving circuit, including N levels of shift registers cascaded with each other, N≥2;
• and
• a shift register of the N levels of the shift registers including:
• a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the second node and the signal of the fourth node and including a first transistor and a second transistor, the third voltage signal being a high level signal, and the fourth voltage signal being a low level signal, wherein:
• in the N levels of the shift registers of the driving circuit, a signal of the fourth node of an M-th level of the shift registers is connected to an input signal terminal of an (M+1)-th level of the shift registers as an input signal of the (M+1)-th level of the shift registers, 1≤M≤M+1≤N;
• the first transistor and the second transistor are P-type transistors, a source of the first transistor is connected to the third voltage signal, a drain of the first transistor is connected to the output signal, a gate of the first transistor is connected to the fourth node, a source of the second transistor is connected to the fourth voltage signal, a drain of the second transistor is connected to the output signal, and a gate of the second transistor is connected to the second node, or the source of the first transistor is connected to the third voltage signal, the drain of the first transistor is connected to the output signal, the gate of the first transistor is connected to the second node, the source of the second transistor is connected to the fourth voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the fourth node;
• or
• the first transistor and the second transistor are N-type transistors, the source of the first transistor is connected to the fourth voltage signal, the drain of the first transistor is connected to the output signal, the gate of the first transistor is connected to the fourth node, the source of the second transistor is connected to the third voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the second node, or the source of the first transistor is connected to the fourth voltage signal, the drain of the first transistor is connected to the output signal, the gate of the first transistor is connected to the second node, the source of the second transistor is connected to the third voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the fourth node.

A display device, comprising a display panel including:

• a driving circuit, including N levels of shift registers cascaded with each other, N≥2;
• and
• a shift register of the N levels of the shift registers including:
• a third control unit, configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal;
• and
• a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node and including a first transistor and a second transistor, the third voltage signal being a high level signal, and the fourth voltage signal being a low level signal, wherein:
• the first transistor and the second transistor are P-type transistors, a source of the first transistor is connected to the third voltage signal, a drain of the first transistor is connected to the output signal, a gate of the first transistor is connected to the fourth node, a source of the second transistor is connected to the fourth voltage signal, a drain of the second transistor is connected to the output signal, and a gate of the second transistor is connected to the second node, or the source of the first transistor is connected to the third voltage signal, the drain of the first transistor is connected to the output signal, the gate of the first transistor is connected to the second node, the source of the second transistor is connected to the fourth voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the fourth node;
• or
• the first transistor and the second transistor are N-type transistors, the source of the first transistor is connected to the fourth voltage signal, the drain of the first transistor is connected to the output signal, the gate of the first transistor is connected to the fourth node, the source of the second transistor is connected to the third voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the second node, or the source of the first transistor is connected to the fourth voltage signal, the drain of the first transistor is connected to the output signal, the gate of the first transistor is connected to the second node, the source of the second transistor is connected to the third voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the fourth node.