# US 12,079,555 B2 · Automated circuit generation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,079,555 B2 - Document ID: US12079555B2 - Status: Granted - Kind: B2 - Application number: 18/314,004 - Filed: 2023-05-08 - Published: 2023-09-07 - Granted: 2024-09-03 - Earliest claimed: 2019-05-30 - Assignees: Celera Corporation - Applicants: Celera, Inc. - Inventors: Calum MacRae; Jim LoCascio; Karen Mason; John Mason; Richard Philpott; Muhammed Abid Hussain - Web page: https://patentgrep.com/patent/US12079555B2 ## CPC - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/38: Circuit design at the mixed level of analogue and digital signals - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/373: Design optimisation - G06F 2111/12: Symbolic schematics - G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits. ## Claims ### Claim 1 A computer-implemented method of generating a circuit comprising: generating a first model of a circuit to be generated; generating circuit specification parameters corresponding to the first model; selecting a plurality of sub-circuit schematics based on the circuit specification parameters; and combining the sub-circuit schematics to form a circuit schematic for the circuit to be generated, wherein the combined sub-circuit schematics form a transistor level model that corresponds to the first model. ### Claim 2 (depends on 1) The method of claim 1, wherein the first model is a behavioral model. ### Claim 3 (depends on 2) The method of claim 2, wherein the first model comprises a plurality of parameterized functional circuit components each having a behavioral model corresponding to parameters associated with a particular parameterized functional circuit component, and wherein the transistor level model comprises a plurality of transistor level schematics corresponding to the plurality of parameterized functional circuit components. ### Claim 4 (depends on 1) The method of claim 1, wherein a plurality of behavioral level simulations of the first model substantially matches a corresponding plurality of transistor level simulations for the transistor level model. ### Claim 5 (depends on 1) The method of claim 1, wherein the first model is configurable based on the circuit specification parameters to produce a plurality of behaviors for the first model, and wherein simulations for the first model and the transistor level model substantially match when the first model and the transistor level model have the same parameters. ### Claim 6 (depends on 1) The method of claim 1, wherein the sub-circuit schematics comprise predefined analog sub-circuit schematics. ### Claim 7 (depends on 1) The method of claim 1, further comprising: converting the circuit schematic to a plurality of layout instances; and positioning the layout instances based on a layout script to produce a circuit layout. ### Claim 8 A computer system for generating a circuit comprising: one or more processors; and a non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by the computer system, cause the computer system to perform a method comprising: generating a first model of a circuit to be generated; generating circuit specification parameters corresponding to the first model; selecting a plurality of sub-circuit schematics based on the circuit specification parameters; and combining the sub-circuit schematics to form a circuit schematic for the circuit to be generated, wherein the combined sub-circuit schematics form a transistor level model that corresponds to the first model. ### Claim 9 (depends on 8) The computer system of claim 8, wherein the first model is a behavioral model. ### Claim 10 (depends on 9) The computer system of claim 9, wherein the first model comprises a plurality of parameterized functional circuit components each having a behavioral model corresponding to parameters associated with a particular parameterized functional circuit component, and wherein the transistor level model comprises a plurality of transistor level schematics corresponding to the plurality of parameterized functional circuit components. ### Claim 11 (depends on 8) The computer system of claim 8, wherein a plurality of behavioral level simulations of the first model substantially matches a corresponding plurality of transistor level simulations for the transistor level model. ### Claim 12 (depends on 8) The computer system of claim 8, wherein the first model is configurable based on the circuit specification parameters to produce a plurality of behaviors for the first model, and wherein simulations for the first model and the transistor level model substantially match when the first model and the transistor level model have the same parameters. ### Claim 13 (depends on 8) The computer system of claim 8, wherein the sub-circuit schematics comprise predefined analog sub-circuit schematics. ### Claim 14 (depends on 8) The computer system of claim 8, further comprising: converting the circuit schematic to a plurality of layout instances; and positioning the layout instances based on a layout script to produce a circuit layout. ### Claim 15 A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer system, cause the computer system to: generate a first model of a circuit to be generated; generate circuit specification parameters corresponding to the first model; select a plurality of sub-circuit schematics based on the circuit specification parameters; and combine the sub-circuit schematics to form a circuit schematic for the circuit to be generated, wherein the combined sub-circuit schematics form a transistor level model that corresponds to the first model. ### Claim 16 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the first model is a behavioral model. ### Claim 17 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the first model comprises a plurality of parameterized functional circuit components each having a behavioral model corresponding to parameters associated with a particular parameterized functional circuit component, and wherein the transistor level model comprises a plurality of transistor level schematics corresponding to the plurality of parameterized functional circuit components. ### Claim 18 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein a plurality of behavioral level simulations of the first model substantially matches a corresponding plurality of transistor level simulations for the transistor level model. ### Claim 19 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the first model is configurable based on the circuit specification parameters to produce a plurality of behaviors for the first model, and wherein simulations for the first model and the transistor level model substantially match when the first model and the transistor level model have the same parameters. ### Claim 20 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the sub-circuit schematics comprise predefined analog sub-circuit schematics.