Wide-bandgap semiconductor layer characterization

A method of characterizing a compound semiconductor material, comprising;

• providing a substrate which contains a capacitor structure including a layer stack of a first electrode as embodied as a conductive material layer, a node dielectric as embodied as a dielectric material layer, and a second electrode as embodied as a compound semiconductor material layer;
• disposing a tip of a mercury probe on a top surface of the compound semiconductor material layer;
• generating a set of multiple alternating-current (AC) capacitance curves of the layer stack that represents a change in AC capacitance as a function of a change in a direct-current (DC) bias voltage across the conductive material layer and the compound semiconductor material layer by applying a combination of the DC bias voltage and a sinusoidal alternating-current (AC) perturbation voltage across the layer stack, wherein the multiple AC capacitance curves are generated using different frequencies for the sinusoidal AC perturbation voltage;
• and
• determining a structural parameter of the compound semiconductor material layer which is selected from porosity, crystallinity, stoichiometry, and thickness by correlating observed features within the set of multiple AC capacitance curves with the structural parameter using a database containing information on previously-established correlation between features among sets of multiple AC capacitance curves and structural parameters of a reference compound semiconductor material layer having a same base composition as the compound semiconductor material layer in the layer stack.

A method of characterizing a compound semiconductor material, comprising;

• depositing a dielectric metal oxide layer over a conductive material layer;
• depositing a compound semiconductor material layer on the dielectric metal oxide layer, whereby a wafer which contains a capacitor structure including a vertical stack of a first electrode as embodied as the conductive material layer, a node dielectric as embodied as the dielectric metal oxide layer, and a second electrode as embodied as the compound semiconductor material layer;
• disposing a tip of a mercury probe on a top surface of the compound semiconductor material layer;
• generating a set of multiple alternating-current (AC) capacitance curves of the layer stack that represents a change in AC capacitance as a function of a change in a direct-current (DC) bias voltage across the conductive material layer and the compound semiconductor material layer by applying a combination of the DC bias voltage and a sinusoidal alternating-current (AC) perturbation voltage across the layer stack, wherein the multiple AC capacitance curves are generated using different frequencies for the sinusoidal AC perturbation voltage;
• and
• determining a structural parameter of the compound semiconductor material layer which is selected from porosity, crystallinity, stoichiometry, and thickness by correlating observed features within the set of multiple AC capacitance curves with the structural parameter using a database containing information on previously-established correlation between features among sets of multiple AC capacitance curves and structural parameters of a reference compound semiconductor material layer having a same base composition as the compound semiconductor material layer in the layer stack.