3D stacked integrated circuits having failure management
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
Estimating the term…
Abstract
A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
Claims29
An integrated circuit device, comprising:
- a plurality of integrated circuit dies configured in a stack, wherein memory cells and logic circuits are formed on the plurality of integrated circuit dies, wherein the stack is partitioned into a plurality of columns that are perpendicular to the plurality of integrated circuit dies;
- and
- routes configurable to bypass at least a part of a respective column in the plurality of columns and re-route functionality of the respective column to at least a part of a different column of the plurality of columns.
An integrated circuit, comprising:
- a plurality of integrated circuit dies configured in a three-dimensional stack, wherein memory cells are formed on at least a first one of the plurality of integrated circuit dies, and logic circuits are formed on at least a second one of the plurality of integrated circuit dies, wherein the three-dimensional stack is configured into a plurality of columns, wherein at least one of the plurality of columns comprises a memory cell and a logic circuit;
- and
- routes configurable to bypass at least a part of a respective column in the plurality of columns and re-route functionality.
An integrated circuit, comprising:
- a three-dimensional stack of integrated circuit dies, wherein a memory cell is formed on a first integrated circuit die of the three-dimensional stack of integrated circuit dies, and wherein a logic circuit is formed on a second integrated circuit die of the three-dimensional stack of integrated circuit dies, wherein the three-dimensional stack comprises one or more columns, wherein at least one column of the one or more columns comprises the memory cell and the logic circuit;
- and
- routes configurable to bypass at least a part of a respective column in the one or more columns by a re-route functionality.
Dependencies are inferred from the claim text.