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US 12,073,269 B2Granted
Switched-capacitor integrators with improved flicker noise rejection
AssigneeAnalog Devices International Unlimited Company
InventorRoberto S. Maurino
Life of this patent
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Abstract
An example SC integrator can include first and second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. The SC integrator can be configured for adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at one or more cycles of a master clock and can be configured for keeping the time distance/delay between those samples relatively small across a range of master clock frequencies.
Claims20
An electronic device, configured to receive an input signal at an input and to generate an output signal at an output, the electronic device comprising:
- a first capacitor;
- a second capacitor;
- an amplifier, having a positive input port and a negative input port;
- a third capacitor, coupled to an output of the amplifier;
- and
- a switching arrangement, configured to:
- configure the first capacitor to accumulate a first charge during a first time period, the first charge being indicative of the input signal,
- configure the second capacitor to accumulate a second charge during a second time period, the second charge being indicative of the input signal,
- configure the third capacitor to integrate a third charge during a third time period by coupling the first capacitor to one of the positive input port and the negative input port of the amplifier, where the third charge is indicative of the first charge, where the third time period does not overlap with the first time period, and
- configure the third capacitor to integrate a fourth charge during a fourth time period by coupling the second capacitor to another one of the positive input port and the negative input port of the amplifier, where the fourth charge is indicative of the second charge, where the fourth time period does not overlap with the second time period and does not overlap with the third time period,
- wherein the third capacitor is configured to accumulate the fourth charge in addition to the third charge or vice versa, and wherein the output signal is based on a sum of the third charge and the fourth charge accumulated by the third capacitor;
- wherein a time difference between an end of the third time period and an end of the fourth time period is less than half of a period of a master clock configured to time operation of at least portions of the electronic device.
9 more elements
A switched-capacitor (SC) integrator, comprising:
- a charging circuit, comprising an input, coupled to an input signal, and further comprising an output, a plurality of switches, a first capacitor, and a second capacitor;
- an amplifier, having a differential input and a differential output;
- an integrating capacitor;
- and
- a chopper circuit, configured to be either in a first state or in a second state, where:
- in the first state, the chopper circuit couples the output of the charging circuit to a positive input of the differential input of the amplifier and couples a negative output of the differential output of the amplifier to the integrating capacitor, and
- in the second state, the chopper circuit couples the output of the charging circuit to a negative input of the differential input of the amplifier and couples a positive output of the differential output of the amplifier to the integrating capacitor, wherein the plurality of switches is configured to:
- couple the first capacitor to the input and de-couple the first capacitor from the output of the charging circuit during a first phase to enable the first capacitor to accumulate a first charge indicative of the input signal sampled on the first capacitor during the first phase,
- couple the second capacitor to the input and de-couple the second capacitor from the output of the charging circuit during a second phase to enable the second capacitor to accumulate a second charge indicative of the input signal sampled on the second capacitor during the second phase, where the second phase at least partially overlaps with the first phase,
- couple the first capacitor to the output of the charging circuit and de-couple the first capacitor from the input during a third phase, where the third phase starts after the first charge has been accumulated in the first capacitor and where the chopper circuit is in the first state at an end of the third phase, and
- couple the second capacitor to the output of the charging circuit and de-couple the second capacitor from the input during a fourth phase, where the fourth phase starts after the second charge has been accumulated in the second capacitor and where the chopper circuit is in the second state at an end of the fourth phase.
8 more elements
A switched-capacitor (SC) integrator, comprising:
- a first capacitor;
- a second capacitor;
- an amplifier;
- a third capacitor, coupled to an output of the amplifier;
- and
- a switching arrangement, configured to, during a time period of a single cycle of a master clock:
- enable the first capacitor to accumulate a first charge, indicative of a sample of an input signal accumulated during a first time period,
- enable the second capacitor to accumulate a second charge, indicative of a sample of the input signal accumulated during a second time period, and
- enable the third capacitor to:
- in a third time period, integrate a charge indicative of at least a portion of the sample of the input signal accumulated during the first time period and a sample of a flicker noise at an end of the third time period, and
- in a fourth time period, integrate a charge indicative of at least a portion of the sample of the input signal accumulated during the second time period and an inverted version of the flicker noise at an end of the fourth time period,
- wherein a time difference between the end of the third time period and the end of the fourth time period is independent of a clock cycle of the master clock.
9 more elements
Dependencies are inferred from the claim text.