Jitter noise detector

A noise detection circuit, comprising:

• a first n-type metal-oxide-semiconductor (NMOS) field-effect-transistor (FET) configured to receive a clock signal;
• a second NMOS FET configured to receive a reference clock signal;
• and
• a latch circuit, coupled to the first NMOS FET at a first node and coupled to the second NMOS FET at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on a timing difference between transition edges of the clock signal and the reference clock signal,
• wherein when the timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold, the latch circuit is configured to latch the logic states of the voltage levels at the first and second nodes.

A method, comprising:

• receiving a clock signal and a reference clock signal, wherein at least a transition edge of the clock signal is deviated from a transition edge of the reference clock signal by a timing difference;
• receiving the clock signal and the reference clock signal by a first transistor and a second transistor, respectively, to start either discharging or charging voltage levels at drains of the first and second transistors at different times;
• and
• latching, by a latch circuit coupled to the first transistor at a first node and coupled to the second transistor at a second node, respective logic states of the voltage levels at the drains of the first and second transistors when the timing difference is greater than a pre-defined timing offset threshold,
• wherein when the timing difference between transition edges of the clock signal and the reference clock signal exceeds the pre-defined timing offset threshold, the latch circuit is configured to latch the logic states of the voltage levels at the first and second nodes.