Memory cell, memory device manufacturing method and memory device operation method thereof

An integrated memory cell including:

• a first memory cell;
• and
• an embedded second memory cell, serially coupled to the first memory cell,
• wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell;
• the embedded second memory cell is formed at a bottom of a contact, or formed at a top or a bottom of a via;
• and
• the embedded second memory cell is embedded in a source/drain region of the first memory cell, a top surface of the embedded second memory cell is above a top surface of the source/drain region, and a bottom surface of the embedded second memory cell is below the top surface of the source/drain region.