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US 12,068,730 B2Granted
Trimming operational amplifiers
AssigneeTexas Instruments Incorporated
InventorsVadim Valerievich Ivanov, Munaf Hussain Shaik, Srinivas Kumar Pulijala, Patrick Forster, Jerry Lee Doorenbos
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Abstract
Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.
Claims24
A system comprising:
- a plurality of operational amplifiers, each operational amplifier of the plurality of operational amplifiers having individually adjustable operational parameters, and
- a trimming circuit coupled to the plurality of operational amplifiers;
- wherein the trimming circuit comprises successive approximation register (SAR) logic;
- wherein the SAR logic is configured to determine for each operational amplifier an associated memory value;
- wherein the trimming circuit is configured to change the adjustable operational parameters of each operational amplifier based on the associated memory values.
2 more elements
An integrated circuit comprising:
- a successive approximation register (SAR) logic having a first input, a second input, first output and a second output wherein the first input of the SAR logic is configured to be coupled to an output of a first operational amplifier and a second input of the SAR logic is configured to be coupled to the output of a second operational amplifier;
- a first digital-to-analog converter (DAC) having an input and an output wherein the input of the first DAC is coupled to the first output of the SAR logic and the output of the first DAC is configured to generate a first trim signal;
- and
- a second digital-to-analog converter (DAC) having an input and an output wherein the input of the second DAC is coupled to the second output of the SAR logic and the output of the second DAC is configured to generate a second trim signal.
1 more element
An apparatus comprising:
- an integrated circuit (IC) including:
- a first operational amplifier having an inverting and non-inverting input, a trim input, and an output;
- and
- a second operational amplifier having an inverting and non-inverting input, a trim input, and an output;
- and
- a trimming circuit including:
- a successive approximation register (SAR) logic having a first input, a second input, a first output, and a second output, the first input couplable to the output of the first operational amplifier, the second input couplable to the output of the second operational amplifier;
- a first digital-to-analog converter (DAC) having an input coupled to the first output of the SAR logic, and having a trim output couplable to the trim input of the first operational amplifier;
- and
- a second DAC having an input coupled to the second output of the SAR logic, and having a trim output couplable to the trim input of the second operational amplifier.
7 more elements
Dependencies are inferred from the claim text.