Backside via with a low-k spacer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Yu Huang, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
Life of this patent
Estimating the term…
Abstract
A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.
Claims20
A method, comprising:
- receiving a workpiece comprising:
- a plurality of nanostructures disposed over a substrate, and
- a source/drain feature in contact with sidewalls of the plurality of nanostructures and disposed over a semiconductor plug extending into the substrate,
- wherein the workpiece comprises a bottom surface adjacent to the substrate and a top surface away from the substrate;
- forming a hard mask over the bottom surface to cover the semiconductor plug, wherein the hark mask is wider than a bottom surface of the semiconductor plug such that a vertical projection area of the semiconductor plug falls within a vertical projection area of the hard mask;
- etching the substrate from the bottom surface of the workpiece to form a dielectric opening using the hard mask as a mask, such that a portion of the substrate covered by the hard mask remains;
- forming a backside dielectric layer in the dielectric opening;
- replacing the semiconductor plug with a backside contact;
- and
- selectively removing the remaining portion of the substrate to form a gap therein.
A semiconductor device, comprising:
- two stacks of channel members;
- a source/drain feature extending between the two stacks of channel members along a direction;
- a source/drain contact disposed under and electrically coupled to the source/drain feature;
- two gate structures over and interleaved with the two stacks of channel members;
- a low-k spacer horizontally surrounding the source/drain contact;
- a dielectric layer horizontally surrounding the low-k spacer;
- an insulation layer disposed under the source/drain contact;
- and
- a backside power rail embedded in the insulation layer and electrically connected to the source/drain contact.
A semiconductor device, comprising:
- a channel region;
- a source feature and a drain feature sandwiching the channel region along a direction;
- a gate structure over the channel region;
- a dielectric layer under the channel region and the drain feature;
- a source contact disposed directly under the source feature;
- and
- an air gap disposed between the dielectric layer and the source contact.
Dependencies are inferred from the claim text.