Analog-to-digital conversion systems and methods with pulse generators

An imaging system comprising:

• an analog-to-digital converter (ADC) comprising:
• an integrator configured to:
• selectively receive, as an integrator input signal, a detector signal, a first reference signal, or a second reference signal;
• generate an integrator output signal based on the integrator input signal by:
• generating the integrator output signal based on the detector signal for a first duration of time;
• generating the integrator output signal based on the first reference signal for a second duration of time after the first duration of time;
• and
• generating the integrator output signal based on the second reference signal for a third duration of time after the second duration of time;
• a first comparator configured to generate a first comparator output signal based on the integrator output signal and a third reference signal, wherein the first comparator output signal is associated with a first state or a second state;
• a first pulse generator coupled to the first comparator, wherein the first pulse generator is configured to generate a first pulse signal in response to a transition of the first comparator output signal from the first state to the second state;
• and
• a memory device coupled to the first pulse generator, wherein the memory device is configured to capture a first counter value from a first counter circuit in response to the first pulse signal, and wherein the first counter value is associated with the detector signal.

A method for analog-to-digital conversion comprising:

• selectively receiving, by an integrator as an integrator input signal, a detector signal or a first reference signal;
• generating, by the integrator, an integrator output signal based on the integrator input signal;
• generating, by a first comparator, a first comparator output signal based on the integrator output signal and a second reference signal, wherein the first comparator output signal is associated with a first state or a second state;
• in response to a transition of the first comparator output signal from the first state to the second state, generating, by a first pulse generator coupled to the first comparator, a first pulse signal;
• and
• in response to the first pulse signal, capturing, by a memory device coupled to the first pulse generator, a first counter value from a first counter circuit, wherein the first counter value is associated with the detector signal, wherein the memory device comprises a switch and a latch, wherein the switch is coupled to the first pulse generator and is configured to close in response to the first pulse signal, and wherein the latch is configured to receive at least a portion of the first counter value when the switch is closed.