Coding and modulation method, demodulation and decoding method, apparatus, and device

A coding and modulation apparatus, comprising:

• at least one non-transitory memory, configured to store program instructions;
• an input interface configured to obtain K to-be-encoded bits and a modulation scheme, wherein K is an integer greater than or equal to 1;
• at least one processor coupled to the receiver and the at least one non-transitory memory, wherein when executing the program instructions, the at least one processor is configured to:
• encode the K to-be-encoded bits based on M bit levels of the modulation scheme, to obtain M′ code blocks, wherein M′<M, a code length of an ith code block is Ni, and Ni=Mi*N, wherein Mi is a quantity of bit levels corresponding to the ith code block, N is a symbol block length, i is an integer from 1 to M′, and Σi=1i=M′(Mi)=M, and wherein a quantity of information bits comprised in the ith code block is Ki, Σi=1i=M′(Ki)=K, and M, M′, N, Ni, Mi, and Ki are all positive integers;
• and
• modulate the M′ code blocks according to a mapping relationship between the M′ code blocks and the M bit levels, to obtain a modulated symbol sequence, wherein a code block having a code length of Mi*N corresponds to Mi bit levels in the mapping relationship;
• and
• an output interface coupled to the at least one processor and configured to output the modulated symbol sequence.

A demodulating and decoding apparatus, comprising:

• at least one non-transitory memory, configured to store program instructions;
• an input interface configured to
• obtain N modulated symbols corresponding to M′ code blocks, wherein M′<M, M is a quantity of bit levels of a modulation scheme, N is a symbol block length, a code length of an ith code block is Ni, N=Mi*N, Mi is a quantity of bit levels corresponding to the ith code block, i is an integer from 1 to M′, Σi=1i=M′(Mi)=M, and M, M′, N, Ni, and Mi are all positive integers;
• and
• at least one processor coupled to the at least one non-transitory memory and the receiver, wherein when executing the program instructions, the at least one processor is configured to:
• sequentially demodulate and decode the M′ code blocks based on the N modulated symbols, to obtain decoding results of the M′ code blocks.