Clock scheme circuit and a mobile double data rate memory using the clock scheme circuit
AssigneeMediatek Inc.
InventorGuan-Yu Su
Life of this patent
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Abstract
A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.
Claims15
A clock scheme circuit, comprising:
- a global clock generator and a global clock trace;
- and
- a local clock generator, coupled to the global clock generator through the global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal,
- wherein:
- the local clock generator comprises a frequency multiplier;
- the local clock generator generating the local clock signal uses the frequency multiplier to multiply a frequency of the global clock signal by a multiplication factor of not less than 1;
- the global clock generator uses multiple phase-locked loops to generate multiple global clock candidates;
- and
- a clock gating multiplexer is provided on the global clock trace to select one of the global clock candidates as the global clock signal to be transferred to the local clock generator.
Dependencies are inferred from the claim text.