Chip-to-chip interconnect with a layered communication architecture

A method, comprising:

• configuring a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit;
• configuring a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit;
• and
• establishing an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control that updates a total blocks sent counter based on a block size of a sent packet, wherein the interconnect between the first integrated circuit package and the second integrated circuit package includes a direct chip-to-chip connection configured to carry the ethernet-based communication as a direct chip-to-chip communication between the first integrated circuit package as a first chip and the second integrated circuit package as a second chip.

A system, comprising:

• a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit;
• a second integrated circuit package including a second group of one or more artificial intelligence processing units and a switch communication unit, wherein the switch communication unit is configured to provide an intermediate connection point between the first integrated circuit package and at least a third integrated circuit package;
• and
• an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the switch communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control that updates a total blocks sent counter based on a block size of a sent packet, wherein the interconnect between the first integrated circuit package and the second integrated circuit package includes a direct chip-to-chip connection configured to carry the ethernet-based communication as a direct chip-to-chip communication between the first integrated circuit package as a first chip and the second integrated circuit package as a second chip.