Multi-dimensional network interface
AssigneeArm Limited
InventorsRainer Herberholz, Supreet Jeloka
Life of this patent
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Abstract
Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.
Claims14
A device comprising:
- an integrated circuit with multiple tiers including a first tier and a second tier arranged vertically in a stacked configuration, wherein the first tier has first functional components, and wherein the second tier has second functional components;
- and
- a three-dimensional (3D) connection at least partially disposed within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier, wherein a clock phase used to launch or capture network lane signals of the 3D connection is configured to be adjusted differently for timing paths associated with the signals based on at least a direction of communication of the timing paths.
A method comprising:
- providing an integrated circuit with multiple tiers including a first tier and a second tier arranged vertically in a stacked configuration, the first tier having first functional components, and the second tier having second functional components;
- providing a three-dimensional (3D) connection at least partially disposed within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier, wherein a clock phase used to launch or capture network lane signals of the 3D connection is configured to be adjusted differently for timing paths associated with the signals based on at least a direction of communication of the timing paths;
- and
- manufacturing, or causing to be manufactured, the integrated circuit with the multiple tiers and the communication network.
Dependencies are inferred from the claim text.