Processing system, related integrated circuit, device and method

A processing system comprising:

• a digital processing core comprising a microprocessor programmable via software instructions;
• a memory controller configured to read the software instructions from a non-volatile memory;
• a communication system connecting the processing core to the memory controller and a resource;
• a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring the operation of the processing core, the memory controller, or the resource;
• a fault collection and error management circuit configured to:
• receive the plurality of error signals from the plurality of safety monitoring circuits, and
• generate one or more reaction signals as a function of the plurality of error signals;
• a reset circuit configured to selectively reset the processing system;
• a diagnostic circuit configured to selectively execute one or more tests of the processing system;
• wherein, in response to switching on the processing system, the processing system is configured to execute the following phases in sequence:
• a reset phase, wherein the reset circuit executes a reset of the processing system,
• a diagnostic phase, wherein the diagnostic circuit executes the one or more tests of the processing system, and
• a software runtime phase, wherein the microprocessor is started and executes software instructions;
• and
• wherein the processing system comprises a hardware connectivity test circuit configured to test, during the diagnostic phase, the connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit, wherein the hardware connectivity test circuit comprises, for each error signal, a circuit configured to selectively assert or de-assert the respective error signal generated by a respective safety monitoring circuit as a function of a respective selection signal, and a control circuit configured to:
• set the selection signals in order to de-assert a first subset of the error signals via the circuit,
• determine whether the respective error signals of the first subset received by the fault collection and error management circuit are de-asserted,
• set the selection signals in order to assert a second subset of the error signals via the circuit,
• determine whether the respective error signals of the second subset received by the fault collection and error management circuit are asserted, and
• in response to determining that at least one of the error signals of the first subset received by the fault collection and error management circuit is not de-asserted or at least one of the error signals of the second subset received by the fault collection and error management circuit is not asserted, set a status signal to a value indicating an error of the connectivity test.

A method of operating a processing system comprising a control circuit, a fault collection and error management circuit, and a plurality of safety monitoring circuits, the method comprising:

• in response to the processing system being powered on, sequentially executing a reset phase, a diagnostic phase, and a software runtime phase;
• and
• executing, by a control circuit of the processing system, the following operations during the diagnostic phase to perform a connectivity test to test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit:
• setting selection signals to de-assert a first subset of error signals generated by the plurality of safety monitoring circuits,
• determining whether the error signals of the first subset received by the fault collection and error management circuit are de-asserted,
• setting the selection signals in order to assert a second subset of the error signals,
• determining whether the error signals of the second subset received by the fault collection and error management circuit are asserted, and
• in response to determining that at least one of the error signals of the first subset is not de-asserted or at least one of the error signals of the second subset is not asserted, setting a status signal to a value indicating an error of the connectivity test.