Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Cheng Wu, Li-Feng Teng
Life of this patent
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Abstract
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
Claims20
A semiconductor device including a non-volatile memory, the non-volatile memory comprising:
- a first dielectric layer disposed on a substrate;
- a floating gate disposed on the first dielectric layer;
- a control gate;
- a select gate;
- an erase gate;
- and
- a second dielectric layer disposed between the floating gate and the control gate, and having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof, wherein:
- the first dielectric layer includes a lower layer made of silicon oxide and an upper layer made of a dielectric material having a dielectric constant higher than the lower layer, and
- the lower layer includes a laterally extending portion that extends under the select gate, as a select gate dielectric layer, and the upper layer does not extend under the select gate.
A semiconductor device comprising:
- a non-volatile memory;
- and
- a logic circuit including a field effect transistor (FET), wherein:
- the non-volatile memory includes:
- a first dielectric layer disposed on a substrate;
- a floating gate disposed on the first dielectric layer;
- a control gate;
- a select gate;
- an erase gate;
- and
- a second dielectric layer disposed between the floating gate and the control gate, and having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof, wherein:
- the first dielectric layer includes a lower layer and an upper layer made of a dielectric material having a dielectric constant higher than silicon nitride,
- a gate dielectric layer of the FET includes a lower layer made of a same material as the lower layer of the first dielectric layer and an upper layer made of a same material as the upper layer of the first dielectric layer, and
- a thickness of the upper layer of the gate dielectric layer of the FET is equal to a thickness of the upper layer of the first dielectric layer.
A non-volatile memory comprising:
- an isolation insulating layer embedded in a semiconductor substrate and separating a memory cell area and a logic circuit area;
- a first dielectric layer disposed on the semiconductor substrate;
- a floating gate disposed on the dielectric layer;
- a control gate;
- an erase gate;
- a select gate;
- a second dielectric layer disposed between the floating gate and the control gate, and having one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof;
- and
- first to third sidewall spacers, wherein:
- the first dielectric layer includes:
- a first-first dielectric layer formed on the substrate;
- and
- a second-first dielectric layer formed on the first-first dielectric layer and including a dielectric material having a dielectric constant higher than silicon nitride,
- the control gate, the erase gate and the select gate includes a conductive layer made of a same material,
- the erase gate and the select gate include a polysilicon layer under the conductive layer, and
- the control gate includes no polysilicon layer.
Dependencies are inferred from the claim text.