ESD protection circuit with isolated SCR for negative voltage operation

A semiconductor device, comprising:

• a p-type semiconductor substrate;
• and
• a semiconductor controlled rectifier including:
• a first n-type doped region;
• a first p-type doped region formed within the first n-type doped region;
• a second p-type doped region formed proximate the first n-type doped region;
• a second n-type doped region formed within the second p-type doped region, wherein:
• the second n-type doped region has a first side abutting a shallow trench isolation structure formed in the second p-doped region and a second side opposite the first side;
• a n-type buried layer formed in the p-type semiconductor substrate below the second p-type doped region and electrically connected to the first n-type doped region, wherein the first n-type doped region extends to the n-type buried layer;
• and
• a silicide blocking layer over a junction between the first n-type doped region and the second p-type doped region.

A semiconductor device, comprising:

• a p-type semiconductor substrate;
• and
• a semiconductor controlled rectifier including:
• a first n-type doped region;
• a first p-type doped region formed within the first n-type doped region;
• a second p-type doped region formed proximate the first n-type doped region;
• a second n-type doped region formed within the second p-type doped region, wherein:
• the second n-type doped region has a first side abutting a shallow trench isolation structure formed in the second p-doped region and a second side opposite the first side;
• an n-type buried layer formed in the p-type semiconductor substrate below the second p-type doped region and electrically connected to the first n-type doped region, wherein the first n-type doped region extends to the n-type buried layer;
• and
• a silicide blocking layer over a junction between the first n-type doped region and the second p-type doped region, wherein the silicide blocking layer is directly on a surface of the p-type semiconductor substrate and comprises a deposited dielectric.