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US 12,057,321 B2Granted
Methods for forming polycrystalline channel on dielectric films with controlled grain boundaries
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorCheng-Hsien Wu
Life of this patent
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Abstract
A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.
Claims20
A semiconductor device, comprising:
- a dielectric layer over a substrate;
- and
- a polycrystalline semiconductor region within a recess of the dielectric layer, the polycrystalline semiconductor region comprising:
- a first crystal grain and a second crystal grain contacting opposite lengthwise sidewalls of the recess;
- a third crystal grain and a fourth crystal grain contacting opposite widthwise sidewalls of the recess;
- a first grain boundary between the first crystal grain and the second crystal grain;
- a second grain boundary between the third crystal grain and the first crystal grain;
- a third grain boundary between the third crystal grain and the second crystal grain;
- a fourth grain boundary between the fourth crystal grain and the first crystal grain;
- and
- a fifth grain boundary between the fourth crystal grain and the second crystal grain;
- a plurality of semiconductor fins in the first crystal grain extending along a lengthwise direction of the recess;
- a gate structure straddling a channel portion of each of the plurality of semiconductor fins;
- and
- source/drain regions on opposite sides of the gate structure.
12 more elements
A semiconductor device, comprising:
- a dielectric layer over a substrate, the dielectric layer comprising a recess therein;
- and
- a polycrystalline semiconductor region within the recess, the polycrystalline semiconductor region comprising a first crystal grain and a second crystal grain contacting opposite lengthwise sidewalls of the recess and a first grain boundary between the first crystal grain and the second crystal grain;
- a first transistor in a first region of the first crystal grain, the first transistor comprising:
- a first semiconductor fin in the first region of the first crystal grain extending along a lengthwise direction of the recess;
- a first gate structure straddling a channel portion of the first semiconductor fin;
- and
- first source/drain regions on opposite sides of the first gate structure;
- a second transistor in a second region of the first crystal grain, the second transistor composing:
- a second semiconductor fin in the first region of the first crystal grain extending along the lengthwise direction of the recess;
- a second gate structure straddling a channel portion of the second semiconductor fin;
- and
- second source/drain regions on opposite sides of the first gate structure;
- a gate contact structure coupled to the first gate structure and the second gate structure;
- first source/drain contact structures coupled to the first source/drain regions;
- and
- second source/drain contact structures coupled to the second source/drain regions.
14 more elements
A semiconductor device, comprising:
- a dielectric layer comprising a plurality of recesses therein;
- a plurality of polycrystalline semiconductor regions in the plurality of recesses, wherein each of the polycrystalline semiconductor regions comprises a first crystal grain and a second crystal grain contacting lengthwise sidewalls of a corresponding recess of the plurality of recesses and a grain boundary between the first crystal grain and the second crystal grain;
- a plurality of semiconductor fins in the first crystal grain extending along a lengthwise direction of the corresponding recess;
- a gate structure straddling a channel portion of each of the plurality of semiconductor fins;
- and
- source/drain regions on opposite sides of the gate structure.
3 more elements
Dependencies are inferred from the claim text.