Wafer level sequencing flow cell fabrication

A method for forming sequencing flow cells, comprising:

• providing a semiconductor substrate covered with a dielectric layer;
• forming a patterned layer on the dielectric layer, the patterned layer having differential surface regions that include alternating first surface regions and second surface regions;
• forming a first covering layer selectively on the first surface regions by exposing the patterned layer to a first material;
• form a second covering layer selectively on the second surface regions and not on the first surface regions, by exposing the patterned layer to a second material, wherein one of the first covering layer and the second covering layer is hydrophobic, and the other one of the first covering layer and the second covering layer is hydrophilic;
• and
• attaching a cover substrate to the semiconductor substrate to form a composite wafer structure that includes a plurality of sequencing flow cells, wherein each sequencing flow cell includes:
• a flow channel between the patterned layer and the cover substrate;
• one or more first surface regions in the patterned layer;
• one or more second surface regions in the patterned layer;
• and
• an inlet and an outlet coupled to the flow channel.

A method for forming sequencing flow cells, comprising:

• on a semiconductor substrate including a patterned layer on a surface of the semiconductor substrate, the patterned layer having differential surface regions that include alternating first surface regions and second surface regions, forming a first covering layer selectively on the first surface regions by exposing the patterned layer to a first material;
• and
• attaching a cover substrate to the semiconductor substrate to form a composite wafer structure that includes a plurality of sequencing flow cells, wherein each sequencing flow cell includes:
• a flow channel between the patterned layer and the cover substrate;
• one or more first surface regions in the patterned layer;
• one or more second surface regions in the patterned layer;
• and
• an inlet and an outlet coupled to the flow channel;
• further comprising forming a plurality of through holes in the semiconductor substrate before attaching the cover substrate, the plurality of through holes configured as inlets and outlets for the plurality of sequencing flow cells.