Issuing instructions on a vector processor
AssigneeMicrosoft Technology Licensing, LLC
InventorsAaron Michael Landy, Skand Hurkat
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a mechanism for issuing instructions in a processor (e.g., a vector processor) implemented as an overlay on programmable hardware (e.g., a field programmable gate array (FPGA) device). Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD). Systems described herein involve an issue component of a processor controller (e.g., a vector processor controller) that enables fast and efficient instruction issue while verifying that structural and data hazards between instructions have been resolved.
Claims20
A method being implemented by a processor as an overlay on programmable hardware, the method comprising:
- receiving, by a control unit, an instruction for execution on at least one functional unit of the processor;
- placing the instruction in an instruction issue queue, the instruction issue queue including a plurality of instructions received by the control unit, and wherein the instruction issue queue includes an indication of a range of instructions that have not been issued;
- applying a first hazard tracker to the instruction to determine a lack of a first type of resource availability for executing the instruction on the at least one functional unit;
- and
- applying a second hazard tracker to the instruction to determine a lack of a second type of resource availability for executing the instruction on the at least one functional unit, the second hazard tracker being applied to the instruction in parallel with the first hazard tracker, and wherein the control unit attempts to issue the instruction prior to at least one of the first hazard tracker and the second hazard tracker confirming availability for executing the instruction on the at least one functional unit.
A method being implemented by a processor as an overlay on programmable hardware, the method comprising:
- receiving, by a control unit, an instruction for execution on at least one functional unit of the processor;
- placing the instruction in an instruction issue queue, the instruction issue queue including a plurality of instructions received by the control unit, and wherein the instruction issue queue includes an indication of a range of instructions that have not been issued;
- applying a first hazard tracker to the instruction to determine a lack of a first type of resource availability for executing the instruction on the at least one functional unit;
- applying a second hazard tracker to the instruction to determine a lack of a second type of resource availability for executing the instruction on the at least one functional unit, the second hazard tracker being applied to the instruction in parallel with the first hazard tracker;
- and
- resetting, based on determining the lack of availability for executing the instruction on the at least one functional unit, at least one issued instruction and modifying the instruction issue queue based on an earliest instruction that has not successfully issued.
A processor implemented as an overlay on programmable hardware, comprising:
- a scalar unit configured to fetch and decode instructions;
- a plurality of lanes comprising functional units thereon configured to execute instructions;
- and
- a control unit being configured to:
- receive, from the scalar unit, an instruction for execution on at least one functional unit of the processor;
- place the instruction in an instruction issue queue, the instruction issue queue including a plurality of instructions received by the control unit, and wherein the instruction issue queue includes an indication of a range of instructions that have not been issued;
- apply a first hazard tracker to the instruction to determine a lack of a first type of resource availability for executing the instruction on the at least one functional unit;
- and
- apply a second hazard tracker to the instruction to determine a lack of a second type of resource availability for executing the instruction on the at least one functional unit, the second hazard tracker being applied to the instruction in parallel with the first hazard tracker, and wherein the control unit attempts to issue the instruction prior to at least one of the first hazard tracker and the second hazard tracker confirming availability for executing the instruction on the at least one functional unit.
Dependencies are inferred from the claim text.