US 12,055,587 B2 · Integrated test circuit, test assembly and method for testing an integrated circuit

Abstract

An integrated circuit includes a ring oscillator circuit and a plurality of logic paths. Each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path. Each logic path, beginning with a first logic path, is assigned a respective subsequent logic path by virtue of the path output connection of the logic path being connected to a data input connection of the input multiplexer of the subsequent logic path. A last logic path of the logic paths is assigned the first logic path as subsequent logic path. For each logic path, the multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, it connects the data input connection of the input multiplexer to the path input connection of the logic path.

Claims20

Dependent claims

An integrated circuit, comprising:

at least one ring oscillator circuit, comprising:
a plurality of logic paths, wherein each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path,
wherein a first logic path of the plurality of logic paths has a path output connection connected to a data input connection of the input multiplexer of a subsequent logic path, and wherein the subsequent logic path has a path output connection connected to a data input connection of the input multiplexer of a last logic path of the plurality of logic paths, and wherein the last logic path has a path output connection connected to a data input connection of the input multiplexer of the first logic path;
and
wherein, for each logic path, the input multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, the input multiplexer connects the data input connection of the input multiplexer to the path input connection of the logic path.

2 more elements

An integrated circuit, comprising:

a first multiplexer comprising a first first multiplexer input, a second first multiplexer input, a first multiplexer output, and a first multiplexer control;
a first logic path comprising a first logic path input and a first logic path output, the first logic path input coupled to the first multiplexer output;
a second multiplexer comprising first second multiplexer input, a second second multiplexer input, a second multiplexer output, and a second multiplexer control, the second multiplexer control coupled to the first multiplexer control and the first second multiplexer input coupled to the first logic path output;
a second logic path comprising a second logic path input and a second logic path output, the second logic path input coupled to the second multiplexer output and the second logic path output coupled to the second first multiplexer input;
a first input scan flip-flop comprising a first input scan flip-flop input and a first input scan flip-flop output, the first input scan flip-flop output coupled to the first first multiplexer input;
and
a second input scan flip-flop comprising a second input scan flip-flop input and a second input scan flip-flop output, the second input scan flip-flop output coupled to the second second multiplexer input.

4 more elements

An integrated circuit, comprising an oscillator circuit, comprising:

a first input scan flip-flop comprising a first input scan flip-flop input and a first input scan flip-flop output;
a first multiplexer comprising a first first multiplexer input, a second first multiplexer input, and a first multiplexer output, the first first multiplexer input coupled to the first input scan flip-flop output;
a first output scan flip-flop comprising a first output scan flip-flop input and a first output scan flip-flop output;
a first logic path comprising a first logic path input and a first logic path output, the first logic path input coupled to the first multiplexer output and the first logic path output coupled to the first output scan flip-flop input;
a second input scan flip-flop comprising a second input scan flip-flop input and a second input scan flip-flop output;
a second multiplexer comprising a first second multiplexer input, a second second multiplexer input, and a second multiplexer output, the first second multiplexer input coupled to the second input scan flip-flop output;
a second output scan flip-flop comprising a second output scan flip-flop input and a second output scan flip-flop output;
a second logic path comprising a second logic path input connection and a second logic path output, the second logic path input connection coupled to the second multiplexer output and the second logic path output coupled to the second output scan flip-flop input;
a first line coupling the second logic path output to the second first multiplexer input;
and
a second line coupling the first logic path output to the first second multiplexer input.

8 more elements

Dependencies are inferred from the claim text.

Integrated test circuit, test assembly and method for testing an integrated circuit

Life of this patent

Integrated test circuit, test assembly and method for testing an integrated circuit

Life of this patent

Abstract

Claims20