SAR ADC and electronic device

A synchronous ADC comprising:

• a first read clock generation circuit connected to a first output terminal and a second output terminal of a dynamic comparator, generating a first signal based on a first comparison result received from the first output terminal and a second comparison result received from the second output terminal;
• a clock pulse generating circuit connected to the operating clock of the dynamic comparator, generating a second signal based on the operating clock;
• and
• a metastable state detection circuit configured to select the first signal to generate a read clock signal to read the first comparison result of the dynamic comparator when it is detected that the first signal includes a read pulse signal, and select the second signal to generate the read clock signal to read the first comparison of the dynamic comparator when the read pulse signal is not detected in the first signal.

An electronic device, comprising:

• An SAR ADC comprising:
• a dynamic comparator including a first output terminal and a second output terminal, the dynamic comparator generates a first comparison result and a second comparison result at the first output terminal and the second output terminal respectively based on an operating clock of the dynamic comparator;
• and
• a read clock generation circuit connected to the first output terminal and the second output terminal, and configured to generate a read clock signal for reading the first or second comparison result based on the first comparison result and the second comparison result received from the dynamic comparator,
• wherein the read clock generation circuit further comprises:
• a signal selection circuit configured to select a read pulse signal generated based on the first comparison result and the second comparison result to generate the read clock signal when the first comparison result and the second comparison result correspond to different levels, and select a clock pulse signal generated based on the operating clock of the dynamic comparator to generate the read clock signal when the first comparison result and the second comparison result correspond to an identical level.