Transconductance amplifier of high linearity and common-mode rejection
AssigneeRealtek Semiconductor Corp.
InventorChia-Liang (Leon) Lin
Life of this patent
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Abstract
A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.
Claims20
A transconductance amplifier comprising:
- a first MOS (metal-oxide semiconductor) transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node;
- a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node;
- a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node;
- a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node;
- and
- a source degeneration network that is placed across the third node and the fourth node and comprises a parallel connection of a source resistor, a fifth MOS transistor controlled by the first voltage, and a sixth MOS transistor controlled by the second voltage.
A transconductance amplifier comprising a first MOS (metal-oxide semiconductor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a source degeneration network, wherein:
- a gate, a source, and a drain of the first MOS transistor connect to a first node, a third node, and a fifth node, respectively;
- a gate, a source, and a drain of the second MOS transistor connect to a second node, a fourth node, and a sixth node, respectively;
- a gate, a source, and a drain of the third MOS transistor connect to the fifth node, a DC (direct-current) node, and the third node, respectively;
- a gate, a source, and a drain of the fourth MOS transistor connect to the sixth node, the DC node, and the fourth node, respectively;
- and
- the source degeneration network is placed across the third node and the fourth node and comprises a parallel connection of a source resistor, a fifth MOS transistor controlled by a first voltage at the first node, and a sixth MOS transistor controlled by a second voltage at the second node.
Dependencies are inferred from the claim text.