Integrated circuit structure with front side signal lines and backside power delivery

An integrated circuit structure, comprising:

• a plurality of gate lines extending over a plurality of semiconductor fin channel structures within a cell boundary, the plurality of gate lines having a pitch;
• a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
• a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch;
• and
• a backside power delivery line beneath the plurality of semiconductor fin channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures within a cell boundary, the plurality of gate lines having a pitch;
• a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
• a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch;
• and
• a backside power delivery line beneath the plurality of semiconductor nanowire stack channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a plurality of gate lines extending over a plurality of semiconductor fin channel structures within a cell boundary, the plurality of gate lines having a pitch;
• a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
• a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch;
• and
• a backside power delivery line beneath the plurality of semiconductor fin channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.