Planar and non-planar FET-based electrostatic discharge protection devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Lin Peng, Han-Jen Yang, Jam-Wem Lee, Li-Wei Chu
Life of this patent
Estimating the term…
Abstract
An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
Claims20
A device, comprising:
- a source region coupled to a first electrical node;
- a drain region coupled to a second electrical node different from the first electrical node;
- and
- an extended drain region disposed between the source and drain regions comprising electrically floating doped regions and gate regions coupled to the second electrical node, the electrically floating doped regions alternating with the gate regions,
- wherein at least one of electrically floating doped regions is coupled to a third electrical node, and
- wherein the first electrical node is connected to a first potential and the second electrical node is connected to a second potential, the second potential being different than the first potential.
A protection device, comprising:
- a substrate with first and second doped regions formed thereon, wherein the first and second doped regions comprise opposite conductivities;
- a source region within the first doped region;
- a drain region within the second doped region;
- and
- spaced apart electrically floating doped regions positioned between the source and drain regions so that an electrically floating doped region from the spaced apart electrically floating doped regions is between the first and second doped regions,
- wherein each spaced apart electrically floating doped region comprises a same conductivity, and
- wherein the source region is connected to a first potential and the drain region and electrically floating doped regions are connected to a second potential, the second potential being different than the first potential.
An integrated circuit (IC), comprising:
- an electrostatic discharge (ESD) protection device comprising:
- a source region coupled to a power rail;
- a drain region coupled to an input/output (I/O) pad;
- and
- a region between the source and drain regions comprising:
- a gate region coupled to the I/O pad;
- electrically floating doped regions;
- and
- a parasitic resistor.
Dependencies are inferred from the claim text.