Vertical semiconductor structure with integrated sampling structure and method for manufacturing same

A method for manufacturing a vertical semiconductor structure with an integrated sampling structure, comprising:

• providing a semiconductor substrate, wherein the semiconductor substrate comprises an N-type base region, the N-type base region comprises a first N-type base region and a second N-type base region, wherein the first N-type base region is used to form a vertical-semiconductor-structure unit cell, and the second N-type base region is used to form a sampling unit cell;
• forming a first trench in the first N-type base region and forming a control region in the first trench;
• forming a P-type well region within the first N-type base region, wherein a depth of the P-type well region extending into the first N-type base region is less than a depth of the first trench extending into the first N-type base region;
• forming a first P-type diffusion region and a second P-type diffusion region within the second N-type base region, wherein an electron channel is formed between the first P-type diffusion region and the second P-type diffusion region;
• forming a P-type ohmic contact region and N-type source regions in an upper part of the P-type well region, wherein the N-type source regions are disposed on two sides of the P-type ohmic contact region;
• forming an N-type ohmic contact region in an upper part of the electron channel;
• forming a first N-type buffer layer below the first N-type base region;
• forming a second N-type buffer layer below the second N-type base region;
• forming a control electrode over the control region;
• forming a first electrode over the P-type ohmic contact region, the N-type source regions, the first P-type diffusion region, and the second P-type diffusion region;
• forming a sampling electrode over the N-type ohmic contact region;
• and forming a second electrode over the first N-type buffer layer and the second N-type buffer layer.