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US 12,046,571 B2Granted
Low temperature bonded structures
AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorsCyprian Emeka Uzoh, Jeremy Alfred Theil, Liang Wang, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
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Abstract
Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
Claims5
A microelectronic assembly, comprising:
- a first substrate having a first surface with a first conductive material embedded therein;
- a second substrate having a second surface with a second conductive material embedded therein;
- the first substrate directly bonded to the second substrate;
- and
- an electrically conductive mass coupling the first conductive material to the second conductive material, wherein the conductive mass comprises a third conductive layer and a fourth conductive layer, wherein a composition of the third conductive layer and/or a composition of the fourth conductive layer is less than 10% of the first conductive material and the second conductive material combined, and wherein the conductive mass is configured to provide a decreased annealing temperature.
2 more elements
Dependencies are inferred from the claim text.