Surface oxidation control of metal gates using capping layer

A method comprising:

• forming a dummy gate stack on a semiconductor fin;
• forming gate spacers on sidewalls of the dummy gate stack;
• forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric;
• removing the dummy gate stack to form a trench between the gate spacers;
• forming a replacement gate stack in the trench;
• depositing a dielectric capping layer, wherein a bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric;
• depositing a second inter-layer dielectric over the dielectric capping layer;
• performing a first etching process to etch the second inter-layer dielectric and the dielectric capping layer to form a contact opening, wherein the first etching process is a continuous etching process that continuously etches the second inter-layer dielectric and the dielectric capping layer, wherein the second inter-layer dielectric and the dielectric capping layer are etched using a same process gas, and wherein the same process gas comprises:
• a first etching gas, wherein the second inter-layer dielectric is etched faster than the dielectric capping layer by the first etching gas;
• and
• a second etching gas, wherein the dielectric capping layer is etched faster than the second inter-layer dielectric by the second etching gas;
• and
• filling the contact opening with a conductive material to form a contact plug.

A method comprising:

• forming a dummy gate stack on a semiconductor fin;
• forming gate spacers on sidewalls of the dummy gate stack;
• depositing a contact etch stop layer, wherein the contact etch stop layer contacts a source/drain region on a side of the dummy gate stack;
• forming a first inter-layer dielectric on the contact etch stop layer, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric;
• removing the dummy gate stack to form a trench between the gate spacers;
• forming a replacement gate stack in the trench;
• depositing a dielectric capping layer, wherein a bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric;
• depositing a second inter-layer dielectric over the dielectric capping layer;
• performing a first etching process to etch the second inter-layer dielectric and the dielectric capping layer to form a contact opening, wherein the second inter-layer dielectric and the dielectric capping layer are etched using a same process gas, and wherein the same process gas comprises:
• a first etching gas, wherein the second inter-layer dielectric is etched faster than the dielectric capping layer by the first etching gas;
• and
• a second etching gas, wherein the dielectric capping layer is etched faster than the second inter-layer dielectric by the second etching gas;
• and
• filling the contact opening with a conductive material to form a contact plug.