Display panel and display device

A display panel, comprising:

• a shift register includes:
• a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal;
• a second control unit, configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal;
• a third control unit, configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node, wherein the third node is connected to the first node, the first voltage signal is a high-level signal and the second voltage signal is a low-level signal;
• and
• a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node, the third voltage signal being a high level signal, and the fourth voltage signal being a low level signal;
• a pixel circuit;
• and
• a driving circuit, comprising the shift register and configured to provide a first driving signal, the first driving signal being used to selectively reset a gate of a driving transistor;
• wherein:
• a voltage absolute value of the first voltage signal is VGH1, a voltage absolute value of the second voltage signal is VGL1, a voltage absolute value of the third voltage signal is VGH2, and a voltage absolute value of the fourth voltage signal is VGL2;
• and
• |VGH1−VGH2|≤|VGL1−VGL2|.

A display device, comprising a display panel including:

• a shift register including:
• a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal;
• a second control unit, configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal;
• a third control unit, configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node, wherein the third node is connected to the first node, the first voltage signal is a high-level signal and the second voltage signal is a low-level signal;
• and
• a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node, the third voltage signal being a high level signal, and the fourth voltage signal being a low level signal;
• a pixel circuit;
• and
• a driving circuit, comprising the shift register and configured to provide a first driving signal, the first driving signal being used to selectively reset a gate of a driving transistor;
• wherein:
• a voltage absolute value of the first voltage signal is VGH1, a voltage absolute value of the second voltage signal is VGL1, a voltage absolute value of the third voltage signal is VGH2, and a voltage absolute value of the fourth voltage signal is VGL2;
• and
• in response to the driving transistor being a P-type transistor, |VGH1-VGH2|≤|VGL1-VGL2|;
• or
• in response to the driving transistor being an N-type transistor, |VGH1-VGH2|>|VGL1-VGL2|.