In-memory computing architecture and methods for performing MAC operations

A multiply-and-accumulate (MAC) device, comprising:

• an array of multi-level memory cells arranged in columns and rows, wherein multi-level memory cells of a same column shared a bit-line and each multi-level memory cell stores a weight;
• a plurality of registers each configured to receive a digital input and coupled to a row of multi-level memory cells, wherein a read operation of the row of multi-level memory cells is initiated based on a state of a bit of the digital input coupled thereto, the read operation causes a weighted bit-line current from each multi-level memory cell that is read, wherein bits of the digital inputs are sequentially shifted from first bits to last bits;
• a plurality of first charge-storage banks each coupled to one bit-line, configured to receive, convert, and scale the weighted bit-line current accumulated along the one bit-line during the read operation into a scaled charge, wherein a scale factor of the scaled charge corresponds to a significance of the bit, wherein the plurality of first charge-storage banks are further configured to accumulate the scaled charge from the first bits to last bits of the digital inputs;
• and
• Analog-to-digital converter (ADC) circuit configured to generate a digital output based on the scaled charge accumulated for each bit-line.

An artificial intelligence (AI) accelerator system, including:

• a plurality of multiply-and-accumulate (MAC) cores, wherein each MAC core is coupled to one another and comprises:
• an array of multi-level memory cells arranged in columns and rows, wherein multi-level memory cells of a same column shared a bit-line and each multi-level memory cell stores a weight;
• a plurality of registers each configured to receive a digital input and coupled to a row of multi-level memory cells, wherein a read operation of the row of multi-level memory cells is initiated based on a state of a bit of the digital input coupled thereto, the read operation causes a weighted bit-line current from each multi-level memory cell that is read, wherein bits of the digital inputs are sequentially shifted from first bits to last bits;
• a plurality of first charge-storage banks each coupled to one bit-line, configured to receive, convert, and scale the weighted bit-line current accumulated along the one bit-line during the read operation into a scaled charge, wherein a scale factor of the scaled charge corresponds to a significance of the bit, wherein the plurality of first charge-storage banks are further configured to accumulate the scaled charge from the first bits to last bits of the digital inputs;
• and
• Analog-to-digital converter (ADC) circuit configured to generate a digital output based on the scaled charge accumulated for each bit-line;
• a processing unit;
• and
• an input/output (I/O) circuitry.