Dynamic processor architecture control
AssigneeVsora
InventorsKhaled Maalej, Trung Dung Nguyen, Julien Schmitt, Pierre-Emmanuel Bernard
Life of this patent
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Abstract
A processor comprising a control unit and a plurality of processing units interacting according to an operating architecture imposed dynamically by the control unit from among at least two of the following architectures: a single instruction multiple data (SIMD) stream architecture, a multiple instruction single data (MISD) stream architecture, and a multiple instruction multiple data (MIMD) stream architecture. The operating architecture is imposed dynamically by the control unit according to: configuration functions included in a machine code, and/or data to be processed and current processing instructions received as input of the processor.
Claims6
A method for compiling a source code comprising the following steps:
- receiving the source code as input,
- searching in the source code:
- for configuration data imposing an operating architecture of a processor,
- for first parts of the source code corresponding to data processing instructions including cascaded sequences of elementary operations, and
- for second parts of the source code corresponding to data processing instructions including elementary operations that are independent of one another,
- the method further comprising the following step:
- compiling the source code into a machine code,
- in a first case where at least one configuration datum imposing the operating architecture of the processor has been identified, and
- in a second case where the first parts of the source code and the second parts of the source code have been identified, wherein the compiling of the source code into the machine code comprises generating the machine code to include a configuration function based on the second case, said configuration function being arranged to dynamically impose on processing units within the processor executing the machine code an architecture adaptation:
- from a single instruction multiple data (SIMD) stream architecture where the processing units within the processor are dynamically configured for the elementary operations that are independent of one another to not directly exchange data, to a multiple instruction single data (MISD) stream architecture for the cascaded sequences of elementary operations where processed data from a first processing unit of the processing units within the processor is copied to a second processing unit of the processing units within the processor, or
- from the MISD stream architecture to the SIMD stream architecture.
Dependencies are inferred from the claim text.