Learning-based high-performance, energy-efficient, fault-tolerant on-chip communication design framework

A Network on Chip (NoC) reconfigurable router assembly comprising:

• a plurality of input ports for receiving a plurality of input data packets from an upstream reconfigurable router assembly;
• a plurality of discrete input decoders each receiving one of the plurality of input data packets from one of said plurality of input ports and providing a decoded input;
• a plurality of input storage buffers, each receiving a decoded input from one of said plurality of input decoders;
• an interconnection device receiving the plurality of decoded input data packets from said plurality of input storage buffers, and providing a plurality of interconnection output data packets;
• a plurality of discrete output encoders each receiving one of said plurality of interconnection output data packets and providing an encoded output data packet;
• a plurality of output ports each receiving the encoded output data packet from one of said plurality of output encoders;
• an error checking encoder encoding source and providing a first encoded error checking output data packet;
• an error checking input storage buffer receiving the first encoded error checking output data packet from said error checking encoder;
• said interconnection device receiving the first error checking encoded output data packet from said error checking input storage buffer and receiving a second error checking encoded output data packet from the upstream reconfigurable router assembly;
• an error checking decoder connected to said interconnection device, receiving the second error checking encoded output, decoding the second error checking encoded output data packet, determining if the second error checking encoded output data packet has error, and sending a retransmit request to the upstream reconfigurable router assembly to retransmit the plurality of input data packets if the second error checking encoded output data packet has error;
• said plurality of output encoders receiving the first error checking encoded output data packet from said interconnection device;
• a discrete fault-tolerant controller coupled to each of said plurality of discrete input decoders and each of said plurality of discrete output encoders, said discrete fault-tolerant controller:
• transmitting a downstream synchronization control signal to a downstream reconfigurable router to synchronize the plurality of downstream input decoders in the downstream reconfigurable router with said plurality of said output encoders of the current reconfigurable router,
• transmitting an upstream synchronization control signal to the upstream reconfigurable router to synchronize said plurality of output encoders in the upstream reconfigurable router with said plurality of input decoders in the current reconfigurable router,
• receiving a downstream synchronization control signal from the upstream reconfigurable router to synchronize said plurality of input decoders of the current reconfigurable router with said plurality of output encoders in the upstream router,
• receiving an upstream synchronization control signal from the downstream reconfigurable router to synchronize said plurality of output encoders of the current reconfigurable router with said plurality of input decoders in the down stream router,
• receiving a downstream control signal from an upstream reconfigurable router and disable said plurality of input decoders in response to the received downstream control signal,
• transmitting a downstream control signal to a downstream reconfigurable router to disable said plurality of input decoders in said downstream reconfigurable router, transmitting an upstream control signal to the upstream reconfigurable router to disable said output encoders of the upstream reconfigurable router, and
• receiving an upstream control signal from a downstream reconfigurable router and disabling said output encoders in response to the received upstream control signal, and
• a discrete processing device configured to select one of a plurality of fault-tolerant operation modes based on reinforcement machine-learning optimization, and controlling operation of said plurality of input decoders and said plurality of output encoders based on the selected fault-tolerant operation mode, wherein the plurality of fault-tolerant operation modes comprise Cyclic Redundancy Check (CRC), Automatic Retransmission Query (ARQ), Single-bit Error Correction and Double-bit Error Detection (SECDED), and Double-bit Error Correction Triple-bit Error Correction (DECTED);
• said processing device further configured to dynamically determine a state of said reconfigurable router assembly based on attributes of said plurality of input ports, said plurality of output ports, said error correction code (ECC) encoder, said error correction code (ECC) decoder, said buffers, or acknowledgement response;
• said processing device further configured to dynamically disable at least one of said plurality of input decoders or at least one of said plurality of output encoders in response to the determined action to operate in the selected fault-tolerant operation mode, and dynamically enable at least one of said plurality of input decoders or at least one of said plurality of output encoders in response to the determined action to operate in the selected fault-tolerant operation mode.