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US 12,040,758 B2Granted
Current sensing circuit with integrated resistor and switch matrix
AssigneeAvago Technologies International Sales Pte. Limited
InventorsRyan Desrosiers, Jay Ackerman, Mark Rutherford
Life of this patent
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Abstract
An integrated circuit for measuring current while receiving wireless power is described. The integrated circuit measures a current across a resistor by an amplifier. A gain of the amplifier is based on a pair of matched upstairs resistors and a pair of matched downstairs resistors. The pair of matched upstairs resistors may include an offset in resistance. The integrated circuit includes a switch matrix with switches coupled between the integrated resistor and the pair of matched upstairs resistors. The offset for the pair of matched upstairs resistors may be measured by selectively controlling the switches.
Claims20
An integrated circuit comprising:
- a first resistor coupled between a first node and a second node;
- wherein the first resistor has a first resistance (Rs);
- wherein the first resistor is configured to carry a first current (Isns) across the first resistor when the first node has a first voltage (Vrect) and the second node has a second voltage (Vmid);
- an amplifier configured to output a third voltage (Vo);
- a second resistor and a third resistor;
- wherein the second resistor and the third resistor each have a second resistance (Rt);
- wherein the second resistor is coupled between the first node and a first input of the amplifier;
- wherein the third resistor is coupled between the second node and a second input of the amplifier;
- a fourth resistor and a fifth resistor;
- wherein the fourth resistor and the fifth resistor each have a third resistance (Rb);
- wherein the fourth resistor is coupled between a first output of the amplifier and ground;
- wherein the fifth resistor is coupled between a second output of the amplifier and ground;
- wherein the third voltage (Vo) is proportional to the third resistance (Rb);
- a switch matrix comprising a first switch (M1) coupled between the first node and the second resistor, a second switch (M2) coupled between the second node and the third resistor, a third switch (M3) coupled between the second node and the second resistor, and a fourth switch (M4) coupled between the first node and the third resistor;
- and
- a processor configured to determine the first current (Isns) based on one or more digital signals of the third voltage (Vo);
- wherein the processor is configured to measure an offset by the first switch (M1), the second switch (M2), the third switch (M3), and the fourth switch (M4);
- wherein the processor is configured to compensate for the offset when determining the first current (Isns).
15 more elements
A system comprising:
- a coil configured to receive wireless power;
- an integrated circuit comprising:
- a rectifier configured to receive alternating current from the coil and generate a first voltage (Vrect);
- a current sense circuit comprising:
- a first resistor coupled between a first node and a second node;
- wherein the first resistor has a first resistance (Rs);
- wherein the first resistor is configured to carry a first current (Isns) across the first resistor when the first node has the first voltage (Vrect) and the second node has a second voltage (Vmid);
- an amplifier configured to output a third voltage (Vo);
- a second resistor and a third resistor;
- wherein the second resistor and the third resistor each have a second resistance (Rt);
- wherein the second resistor is coupled between the first node and a first input of the amplifier;
- wherein the third resistor is coupled between the second node and a second input of the amplifier;
- a fourth resistor and a fifth resistor;
- wherein the fourth resistor and the fifth resistor each have a third resistance (Rb);
- wherein the fourth resistor is coupled between a first output of the amplifier and ground;
- wherein the fifth resistor is coupled between a second output of the amplifier and ground;
- wherein the third voltage (Vo) is proportional to the third resistance (Rb);
- and
- a switch matrix comprising a first switch (M1) coupled between the first node and the second resistor, a second switch (M2) coupled between the second node and the third resistor, a third switch (M3) coupled between the second node and the second resistor, and a fourth switch (M4) coupled between the first node and the third resistor;
- a voltage regulator configured to regulate the second voltage (Vmid);
- and
- a processor configured to determine the first current (Isns) based on one or more digital signals of the third voltage (Vo);
- wherein the processor is configured to measure an offset of the current sense by the first switch (M1), the second switch (M2), the third switch (M3), and the fourth switch (M4);
- wherein the processor is configured to compensate for the offset when determining the first current (Isns);
- and
- a battery charging system.
23 more elements
Dependencies are inferred from the claim text.