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US 12,040,389 B2Granted
Tiled lateral thyristor
AssigneeSilanna Asia Pte Ltd
InventorsVadim Kushner, Nima Beikae
Life of this patent
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Abstract
A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.
Claims17
A thyristor tile comprising:
- first and second PNP tiles, each of which has an N-type base region and a P-type emitter region;
- first and second NPN tiles, each of which has a P-type base region and an N-type emitter region;
- a first interconnect layer that electrically connects the N-type base regions of the first and second PNP tiles;
- a second interconnect layer that electrically connects the P-type base regions of the first and second NPN tiles;
- a third interconnect layer that electrically connects the N-type emitter regions of the first and second NPN tiles;
- and
- a fourth interconnect layer that electrically connects the P-type emitter regions of the first and second PNP tiles;
- wherein:
- each PNP tile is adjacent to both NPN tiles;
- each NPN tile is adjacent to both PNP tiles;
- and
- the first interconnect layer includes first lateral, longitudinal and diagonal traces that electrically connect to the N-type base regions and that surround first island traces that electrically connect to the P-type emitter regions, the N-type emitter regions and the P-type base regions.
9 more elements
A thyristor comprising:
- a plurality of PNP tiles, each of which has first and second N-type base regions and a P-type emitter region;
- a plurality of NPN tiles, each of which has first and second P-type base regions and an N-type emitter region, wherein at least one of the first and second N-type base regions of each PNP tile is also an N-type collector region of an adjacent one of the NPN tiles, and at least one of the first and second P-type base regions of each NPN tile is also a P-type collector region of an adjacent one of the PNP tiles;
- a first interconnect layer that electrically connects the N-type base regions of the PNP tiles and the N-type collector regions of the NPN tiles, the first interconnect layer including first traces that surround the P-type emitter regions, the N-type emitter regions, and the P-type base regions in a first plane vertically offset therefrom;
- a second interconnect layer that electrically connects the P-type base regions of the NPN tiles and the P-type collector regions of the PNP tiles;
- a third interconnect layer that electrically connects the N-type emitter regions of the NPN tiles;
- and
- a fourth interconnect layer that electrically connects the P-type emitter regions of the PNP tiles;
- wherein the PNP tiles and NPN tiles are arranged in an alternating configuration in both rows and columns.
5 more elements
Dependencies are inferred from the claim text.