Distributed processor memory chip with multi-port processor subunits
AssigneeNeuroBlade Ltd.
InventorsElad Sity, Eliad Hillel
Life of this patent
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Abstract
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
Claims24
A distributed processor memory chip, comprising:
- a substrate;
- a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks;
- a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks from among the plurality of discrete memory banks;
- a first communication port configured to establish a communication connection between the distributed processor memory chip and an external entity other than another distributed processor memory chip;
- a second communication port configured to establish a communication connection between the distributed processor memory chip and a first additional distributed processor memory chip;
- and
- a controller configured to schedule data transmissions via at least one of the first and second communication ports, the data transmissions being scheduled at least in part using clock enable signals to control timing of data transmissions through the at least one of the first and second communication ports.
A method of transferring data between a first distributed processor memory chip and a second distributed processor memory chip, the method comprising:
- determining, using a controller associated with at least one of the first distributed processor memory chip and the second distributed processor memory chip, whether a first processor subunit among a plurality of processor subunits disposed on the first distributed processor memory chip is ready to transfer data to a second processor subunit included in the second distributed processor memory chip;
- and
- based on a determination that the first processor subunit is ready to transfer data to the second processor subunit, using a clock enable signal controlled by the controller to schedule a transfer of the data from the first processor subunit to the second processor subunit after determining that the first processor subunit is ready to transfer the data to the second processor subunit.
A memory chip, comprising:
- a substrate;
- a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks;
- a first communication port configured to establish a communication connection between the memory chip and an external entity other than another memory chip;
- a second communication port configured to establish a communication connection between the memory chip and a first additional memory chip;
- and
- a controller configured to schedule data transmissions via at least one of the first and second communication ports, the data transmissions being scheduled at least in part using clock enable signals to control timing of data transmissions through the at least one of the first and second communication ports.
Dependencies are inferred from the claim text.